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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Date 28-31 May 2000

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  • Proceedings of the IEEE 2000 International Symposium on Circuits and Systems [front matter]

    Publication Year: 2000, Page(s):0_1 - 46
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s):0_19 - 0_31
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  • Co-optimization of FFT and FIR in a delayless acoustic echo canceller implementation

    Publication Year: 2000, Page(s):241 - 244 vol.5
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    In application specific implementation of digital signal processing algorithms optimization is important for a low power solution, not only on block level but also between blocks. This paper presents a co-optimization of a fast Fourier transform and a finite impulse response filter in a silicon implementation of an acoustic echo. The optimization gain can be measured in the number of operations an... View full abstract»

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  • A 5 GHz fully integrated VCO in a SiGe bipolar technology

    Publication Year: 2000, Page(s):193 - 196 vol.5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A fully integrated voltage controlled oscillator operating at 5 GHz is presented. The circuit is designed in a SiGe bipolar technology employing three metal layers. The design is based on a fully integrated LC tank using square spiral inductors. The simulated phase noise is -101.4 dBc/Hz at 100 kHz offset. The effect of bias current on phase noise is also examined. It is shown that an optimum bias... View full abstract»

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  • Single chip implementation of the 1.6 kbps speech vocoder

    Publication Year: 2000, Page(s):597 - 600 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch det... View full abstract»

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  • A low-power silicon-on-insulator PWM discriminator for biomedical applications

    Publication Year: 2000, Page(s):277 - 280 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require DC filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good disc... View full abstract»

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  • A high-swing MOS cascode bias circuit for operation at any current level

    Publication Year: 2000, Page(s):489 - 492 vol.5
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    In this paper, we propose a very simple bias circuit that allows for maximum output voltage swing of MOSFET cascode stages. The proposal is valid for any current density and is technology-independent. Starting from the saturation voltage and from the current density of the cascode stage, we determine the aspect ratio of the transistors in the bias circuit in order to maximize the output voltage sw... View full abstract»

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  • A double-talk resistant echo cancellation based on iterative maximal-length correlation

    Publication Year: 2000, Page(s):237 - 240 vol.5
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A novel acoustic echo canceller for speakerphone system based upon iterative maximal length correlation (IMLC) algorithm is proposed. This algorithm is robust to double talk because of the nature of the ML sequence; it also iteratively reduces the far-end speech's effects. This simple structure was found to perform very well. We also perform a rigorous convergence analysis and derive the lower bou... View full abstract»

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  • Optimum Laguerre filter design technique for sigma-delta demodulators

    Publication Year: 2000, Page(s):405 - 408 vol.5
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    As an alternative to conventional FIR filters, an optimal IIR filter architecture based on orthonormal Laguerre functions is proposed for Sigma-Delta (Σ-Δ) demodulators. A Laguerre IIR filter design methodology is presented via the optimization of a quadratic function subject to a linear and a quadratic constraint. An efficient procedure to perform the optimization is discussed. The pr... View full abstract»

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  • Slovenian text-to-speech system

    Publication Year: 2000, Page(s):41 - 44 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper presents a text-to-speech system that is capable of synthesising continuous Slovenian speech. Input text is processed by a series of independent modules. That enables easy improvements of separate parts of the system. The first two modules (text normalization and grapheme-to-phoneme conversion) comprise tasks such as end-of-sentence detection, abbreviation and number expansion, special ... View full abstract»

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  • Focal-plane on-line nonuniformity correction using floating-gate adaptation

    Publication Year: 2000, Page(s):153 - 156 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We develop stochastic adaptive algorithms for on-line correction of spatial nonuniformity in random-access addressable imaging systems. The adaptive architecture is implemented in analog VLSI, integrated with the sensors on the focal plane. Random sequences of address locations selected with predetermined statistics are used to adaptively equalize the intensity distribution at a variable spatial s... View full abstract»

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  • Integrated RF sensors for electronic warfare applications

    Publication Year: 2000, Page(s):189 - 192 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper describes a research effort to develop integrated RF sensors for various electronic warfare applications. The immediate application is to enable a micro air vehicle (MAV) to detect and home in on a radar or other RF emitter. Thus the sensors must be able to detect RF signals in frequency bands of interest, identify RF emitters of interest, and provide bearing information to the selected... View full abstract»

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  • A straightforward design of mismatch-shaped multi-bit ΔΣ D/A systems

    Publication Year: 2000, Page(s):717 - 720 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The paper presents basic rules, which can be easily applied to design of any practical digital-to-analog (D/A) system with any arbitrary type of a dynamic element matching (DEM) characteristic. The proposed approach is general and it can be effectively implemented. A ΔΣ D/A converted design with a second older low-pass mismatch shaped characteristic is discussed in details “step-... View full abstract»

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  • Performance optimization for high-order continuous-time ΣΔ modulators with extra loop delay

    Publication Year: 2000, Page(s):669 - 672 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Extra loop delay in a continuous-time modulator can cause a stability problem, especially when the modulator uses a high-order single-loop architecture and operates at a high sampling rate. This paper investigates the impact of extra loop delay on the performance of high-order (single-loop) modulators. A solution to compensate this delay and thereby optimize performance is proposed in this paper. ... View full abstract»

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  • Frequency domain analysis of double sampling phase-locked loop

    Publication Year: 2000, Page(s):273 - 276 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    Double sampling phase-locked loop (2-SPLL) is used in frequency synthesis. The unique feature of single sampling PLL is that its phase detector (PD) has a very low unwanted periodic output in steady state. In 2-SPLL, a second sample and hold circuit (S&H) is connected in cascade to suppress further the unwanted periodic PD output. However, the absence of a proper baseband model and design equa... View full abstract»

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  • A novel CMOS four quadrant multiplier based on linearization of the long tail differential pair

    Publication Year: 2000, Page(s):485 - 488 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    In this paper, a novel circuit design technique for linearizing differential pairs is proposed. It is shown that the proposed linearized transconductor offers excellent linearity and exceptionally wide operating range which makes it suitable for operating in analog processing applications. PSpice simulation results are given View full abstract»

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  • Design of a chaotic generator using two CNN cells having non-integer order

    Publication Year: 2000, Page(s):233 - 236 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    In this paper a new chaotic system based on two CNN-like cells is presented. Starting from the classical mathematical representation of Cellular Neural Networks, it is shown that the addition of a further parameter like the non-integer order m of each cell may cause the appearance of new complex behaviors. A suitable integer order approximation is therefore proposed and a chaotic circuit derived f... View full abstract»

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  • A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

    Publication Year: 2000, Page(s):261 - 264 vol.5
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    This paper describes a jitter suppression technique for a 2.48832 Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique improves both the jitter generation and the jitter transfer function. The jitter generation can be suppressed by boosting the loop gain in PLL. A suitable jitter transfer function and jitter tolerance can be achieved by optimizing the char... View full abstract»

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  • Multi-grid methods for power grid simulation

    Publication Year: 2000, Page(s):457 - 460 vol.5
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Power grids for sub-micron large integrated circuits are performance limiting factors due to the large power dissipated (e.g. 100 W at 1.8 V). The analysis of such power grids is important in order to predict and possibly improve the performance. Current classical analysis methods are falling behind as grids become ever larger. This paper proposes a new efficient analysis method suitable for both ... View full abstract»

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  • A method for reducing the variation in “on” resistance of a MOS sampling switch

    Publication Year: 2000, Page(s):437 - 440 vol.5
    Cited by:  Papers (14)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    Variation in the “on” resistance of a MOS sampling switch can introduce distortion into the front end of a switched-capacitor filter or analog-to-digital converter. We review three methods commonly used to linearize the resistance of a MOS switch and propose a new technique that addresses their limitations. A practical method for implementation is also suggested View full abstract»

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  • Design of a low-voltage, low-power, wide-tuning integrated oscillator

    Publication Year: 2000, Page(s):629 - 632 vol.5
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    This paper presents the design of a low-voltage, low-power, wide-tuning, monolithic voltage-controlled oscillator (VCO). The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel low-voltage, high performance active inductor. It operates in the 1.1 GHz to 2.1 GHz frequency range while consuming 1 mA from a 2.5 V power supply, with scope for further reduction to 1... View full abstract»

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  • A novel algorithm for edge detection from direction-derived statistics

    Publication Year: 2000, Page(s):37 - 40 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    This paper presents a novel algorithm for edge detection from an image that is corrupted by additive Gaussian noise. The proposed approach uses a criterion for finding pixels where the image gradient is dominated by the noise term. From these pixels, it produces an approximate distribution of the noise gradient magnitude, and then, using this distribution, a threshold for a given false alarm rate ... View full abstract»

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  • 1.4 V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency

    Publication Year: 2000, Page(s):533 - 536 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A four quadrant analogue multiplier that operates with a 1.4 V single supply and 0.6 V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control. Current efficiency and random distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is c... View full abstract»

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  • High-speed/low-power 1-D DWT architectures with high efficiency

    Publication Year: 2000, Page(s):337 - 340 vol.5
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    In this paper, we propose two scalable architecture's (called Arc J and Arc*2) which perform the Discrete Wavelet Transform (DWT) of an N0-sample sequence in only N0/2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT2 parameter is approximately 1/2 of that of already existing devices. These re... View full abstract»

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  • A silicon olfactory bulb oscillator

    Publication Year: 2000, Page(s):397 - 400 vol.5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    This paper presents a low power MOS-VLSI implementation of an oscillator proposed by Freeman (1975) to model a very important component of the olfactory cortex. The model dynamics has time constants in the order of 1/220 (s). To accomplish the long time constants a new filtering technique recently proposed was utilized. All the blocks involving information processing were designed to operate below... View full abstract»

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