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2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

28-31 May 2000

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  • Proceedings of the IEEE 2000 International Symposium on Circuits and Systems [front matter]

    Publication Year: 2000, Page(s):0_1 - 46
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s):0_19 - 0_31
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  • A silicon olfactory bulb oscillator

    Publication Year: 2000, Page(s):397 - 400 vol.5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    This paper presents a low power MOS-VLSI implementation of an oscillator proposed by Freeman (1975) to model a very important component of the olfactory cortex. The model dynamics has time constants in the order of 1/220 (s). To accomplish the long time constants a new filtering technique recently proposed was utilized. All the blocks involving information processing were designed to operate below... View full abstract»

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  • A highly accurate pipelined architecture for a CORDIC ARMA lattice filter

    Publication Year: 2000, Page(s):369 - 372 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper presents a method to improve implementation accuracy of a recently proposed CORDIC ARMA lattice filter. Since the CORDIC ARMA lattice filter algorithm has a problem in its shift sequence, it cannot implement a lattice filter accurately. Therefore, in this paper we apply the shift sequence proposed by Walther without problem to the CORDIC ARMA lattice filter, and then we realize an accur... View full abstract»

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  • A fuzzy membership function circuit in SC technique

    Publication Year: 2000, Page(s):393 - 396 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A new Switched Capacitor Membership Function circuit, which is based on an offset insensitive SC amplifier and presents triangular-shape transcharacteristics, is proposed. Thanks to the SC approach a good precision, which is independent of process tolerances, is achieved. The circuit was realised in a 1.2-μm standard CMOS technology and both simulations and experimental data were carried out. G... View full abstract»

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  • Cross coupled transconductance cell with improved linearity range

    Publication Year: 2000, Page(s):157 - 160 vol.5
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A novel variation of the cross-coupled operational transconductance cell is presented in this paper. The conventional cross-coupled cell has a differential input linearity range that is dependent on the control voltage. The proposed design removes that restriction while allowing the same tunability using the control voltage. Its input may also be single or fully differential unlike the conventiona... View full abstract»

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  • Q-enhancing technique for rf CMOS active inductor

    Publication Year: 2000, Page(s):589 - 592 vol.5
    Cited by:  Papers (17)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A design technique for realising a very-high Q CMOS active inductor operating in the RF-band is described in this paper. The proposed active inductor is based on double-feedback transconductor topology in which negative feedback is used to realise inductive input impedance while positive feedback is employed to produce a negative resistance for canceling the inductor loss, hence an enhancing of th... View full abstract»

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  • Two new VHF tunable CMOS low-voltage linear transconductors and their application to HF GM-C filter design

    Publication Year: 2000, Page(s):173 - 176 vol.5
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Two new CMOS low-voltage linear transconductors for High Frequency (HF) applications are presented. They use tunable floating voltage sources between the input and the transistor gates of each inverter that forms the transconductor proposed by Nauta (1992). Two implementations of the floating batteries are presented. The proposed transconductors operate under constant low voltage supply as low as ... View full abstract»

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  • Architecture driven filter transformations

    Publication Year: 2000, Page(s):601 - 604 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    In this paper, we present the sum of powers-of-two (SPOT) algorithm transformation that results in a high-speed IIR filter architecture by forcing the first few coefficients of lhe denominator polynomial to powers of two or sums of powers of two. The SPOT transform achieves the same result as achieved by conventional pipelining techniques such as scattered look-ahead and minimum order augmentation... View full abstract»

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  • Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers

    Publication Year: 2000, Page(s):697 - 700 vol.5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors View full abstract»

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  • A self-biased low voltage, low power, CMOS transconductor stage

    Publication Year: 2000, Page(s):649 - 652 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    A self-biased CMOS transconductor stage, able to work with a low-voltage supply and low-power dissipation, is proposed. A fully differential configuration in a 0.25 μm minimum lithography technology has been utilized to design the circuit. Paying particular attention to the mismatch problems, a correct sizing of the circuit has been made. With a voltage supply of 1.2 V, the power consumption is... View full abstract»

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  • A new architecture for implementing pipelined ADF

    Publication Year: 2000, Page(s):365 - 368 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    In this paper, we present a new method for the implementation of pipelined finite impulse response (FIR) adaptive digital filter (ADF). The proposed method reduces the length of the critical path, while simultaneously limiting the latency and the maximum delay of the coefficients of the FIR ADF to two and a fourth of the order of the filter, respectively. The latency of the proposed method is also... View full abstract»

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  • Face recognition

    Publication Year: 2000, Page(s):305 - 308 vol.5
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A transform domain face recognition approach is presented. The DCT is coupled with the HMM to achieve a recognition rate of 100% on ORL face database of 40 subjects with 10 images per subject. The recognition time for ORL database is little over 2 Sec. 5 images of a subject are used to train HMM and remaining 5 are used for recognition test. The proposed method is tested on another face data base ... View full abstract»

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  • Focal-plane on-line nonuniformity correction using floating-gate adaptation

    Publication Year: 2000, Page(s):153 - 156 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We develop stochastic adaptive algorithms for on-line correction of spatial nonuniformity in random-access addressable imaging systems. The adaptive architecture is implemented in analog VLSI, integrated with the sensors on the focal plane. Random sequences of address locations selected with predetermined statistics are used to adaptively equalize the intensity distribution at a variable spatial s... View full abstract»

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  • High-speed bipolar MUX modeling and design

    Publication Year: 2000, Page(s):1 - 4 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    This paper presents modeling and optimized design of Current Mode Logic (CML) MUX. Propagation delay models with few terms are presented. The most accurate model has errors lower than 2%. By using the proposed models a design optimization is proposed. In particular, the bias currents which gives the minimum propagation delay are found. Moreover, it is demonstrated that at the cost of a 10% increas... View full abstract»

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  • Area-time efficient serial-serial multipliers

    Publication Year: 2000, Page(s):585 - 588 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    A new serial-serial multiplier is being proposed which requires only N/2 conventional cells for multiplying two N-bit numbers, compared to N cells needed in existing structures. The significant aspect of the new design is that this 50% reduction in hardware has been achieved without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the mu... View full abstract»

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  • Application of dynamic power supply scaling in a low-energy ATM interface

    Publication Year: 2000, Page(s):745 - 748 vol.5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The potential for saving energy by employing dynamic power supply scaling in an ATM (Asynchronous Transfer Mode) interface circuit is analyzed and simulated. Feedback is used to adjust the power supply based on how full the input buffer is. Either a DC-DC converter or multiple supply voltages can be used. Self-timed processing circuitry allows the feedback to control the speed fairly precisely, ev... View full abstract»

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  • High-linear class AB transconductor for high-frequency applications

    Publication Year: 2000, Page(s):169 - 172 vol.5
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    A CMOS voltage to current converter is proposed which is based on a cross-coupled class AB topology. Thanks to its high-linearity and high-frequency performance, the circuit can be used in high-frequency applications such as mixers, IF amplifiers and filters, etc., where linearity is one of the most critical performance parameters. When the proposed circuit is compared with other voltage to curren... View full abstract»

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  • Single chip implementation of the 1.6 kbps speech vocoder

    Publication Year: 2000, Page(s):597 - 600 vol.5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch det... View full abstract»

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  • A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops

    Publication Year: 2000, Page(s):665 - 668 vol.5
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents the design of a 1-GHz transposition memory (TRAM) that is designed in a 3.3-V 0.35-μm CMOS technology. This high-speed TRAM is designed with the DFF-based architecture, and a new true-single-phase pulse-clocked D flip-flop (DFF) is developed to help achieve low power besides the high-speed performance. The new DFF is evolved from the true-single-phase-clocked (TSPC) split-ou... View full abstract»

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  • High-speed high-precision voltage-mode MIN/MAX circuits in CMOS technology

    Publication Year: 2000, Page(s):13 - 16 vol.5
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A new circuit for multiple-input voltage-mode min/max circuits that, unlike conventional implementations, do not have large voltage swings at any of the internal nodes, is discussed. This scheme is characterized by high-speed, high-precision and simple architecture. The proposed circuit exhibits linear complexity with the number of inputs. A test chip prototype with a three-input max circuit has b... View full abstract»

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  • Multi-grid methods for power grid simulation

    Publication Year: 2000, Page(s):457 - 460 vol.5
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Power grids for sub-micron large integrated circuits are performance limiting factors due to the large power dissipated (e.g. 100 W at 1.8 V). The analysis of such power grids is important in order to predict and possibly improve the performance. Current classical analysis methods are falling behind as grids become ever larger. This paper proposes a new efficient analysis method suitable for both ... View full abstract»

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  • A DLL based 10-320 MHz clock synchronizer

    Publication Year: 2000, Page(s):265 - 268 vol.5
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    A clock synchronization scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analog and digital DLLs to align phases of two different frequency clocks. Simulation results represent that the internal clock is synchronized to the reference clock by tracking the dual feedback loop. The whole circuit design was performed using 0.35 μm CMO... View full abstract»

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  • Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages

    Publication Year: 2000, Page(s):445 - 448 vol.5
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Novel common-mode feedback circuits are proposed for use in pseudo-differential switched-capacitor circuits. They can be implemented by incorporating just four additional capacitors (and switches) for an integrator, and only two additional capacitors for a residue gain amplifier. The circuits are applicable to very low-voltage switched-capacitor stages realized in submicron low-voltage CMOS proces... View full abstract»

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  • Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

    Publication Year: 2000, Page(s):561 - 564 vol.5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even if we increase silicon area. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage View full abstract»

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