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Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Date 24-24 May 2000

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Displaying Results 1 - 25 of 131
  • Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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    Freely Available from IEEE
  • Author index

    Page(s): 0_23 - 0_25
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    Freely Available from IEEE
  • Coral-automating the design of systems-on-chip using cores

    Page(s): 109 - 112
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    The reuse of pre-designed and pre-verified IP blocks or cores has been touted as the enabler of large systems-on-chip designs. However, the lack of appropriate tools and the increasing complexity of such cores makes them inherently difficult and error-prone to use. This paper presents a new tool, “Coral”, for the design of systems using cores. Coral is based on a new synthesizable virtual design representation which is automatically synthesized to a real design. Novel algorithms are presented to interconnect cores automatically as well as configure system parameters, such as interrupt maps, DMA channel assignments, etc. Coral significantly reduces the time, complexity and potential for errors associated with SoC integration View full abstract»

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  • An integrated capacitively coupled transformer and its application for RF IC's

    Page(s): 349 - 352
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    This paper describes a low voltage topology that uses a passive element that is described as a “capacitively coupled transformer” (CCT). This structure can be easily implemented using an IC technology that supports both on chip MIM capacitors and high Q-inductors. The structure is used to design a low noise amplifier at 1.9 GHz. The LNA consumes 4 mA of current has a input IP3 of -4.5 dBm, a noise figure of 2.3 dB for a source resistance of 50 Ω, a minimum noise figure of 1.9 dB, and a gain of 10.1 dB. The topology maintains a high linearity without sacrificing noise figure and gain for a supply voltage of 1 V View full abstract»

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  • Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video

    Page(s): 473 - 476
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    We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively View full abstract»

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  • Impact of technology scaling on CMOS RF devices and circuits

    Page(s): 361 - 364
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    In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 μm, 0.25 μm, 0.35 μm, 0.5 μm and 0.8 μm. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 μm for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 μm and 50 μm for the 0.8 μm and 0.18 μm gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 μm and 0.18 μm CMOS processes, respectively. This reduction in current is due to the fact that gm/Ids for a 0.18 μm process is 25 V-1 whereas it is equal to 5 V-1 for a 0.5 μm process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver View full abstract»

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  • Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

    Page(s): 151 - 154
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    We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power μP in both performance and energy consumption. We believe DRLE's scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs View full abstract»

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  • Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture

    Page(s): 135 - 138
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    The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the WarpTM 6.0 software View full abstract»

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  • A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity

    Page(s): 27 - 30
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    A VLSI implementation of an all-digital frequency-agile single-chip quadrature amplitude modulation (QAM) modulator is presented. The proposed chip supports wide variety data rates with diversity in spatial and frequency domain suitable for a wireless modem. The QAM modulator accepts either a parallel or serial bit stream input and assigns these to various QAM symbol formats for transmission. An optimized architecture for the variable modulator supports QAM symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally-flexible IF frequencies up to 70 MHz with four channel beamforming diversity View full abstract»

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  • Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems

    Page(s): 447 - 450
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    This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme View full abstract»

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  • Analysis of jitter due to power-supply noise in phase-locked loops

    Page(s): 443 - 446
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    Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 μm CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model View full abstract»

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  • A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyond

    Page(s): 61 - 64
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    A new fabrication method for embedded DRAM of 0.18 μm generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications View full abstract»

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  • CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

    Page(s): 371 - 374
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    This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85°C. The circuits were fabricated on a generic 0.5 μm digital CMOS process View full abstract»

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  • A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping

    Page(s): 13 - 16
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    A 1 V, 1 mW, 14 bit delta-sigma modulator in a standard CMOS 0.35-μm technology is presented. A modified symmetrical bootstrapped switch is used in order to allow rail-to-rail signal switching. A single-loop third-order topology with an oversampling ratio of 100 achieves a dynamic range of 88 dB, a peak SNR of 87 dB and a peak SNDR of 85 dB in a signal bandwidth of 25 kHz View full abstract»

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  • Field configurable system-on-chip device architecture

    Page(s): 155 - 158
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    Time to market pressures, increasing system complexity, and smaller process geometries, are creating a market vacuum that will be increasingly addressed by an important emerging category of devices: the Configurable System-on-Chip (CsoC). These application specific programmable parts (ASPP) are single chip combinations of microprocessors, memory, dedicated peripheral functions, and embedded programmable logic. They provide unprecedented time-to-market benefits and field customization for the electronic systems of this upcoming decade. Integration of microprocessors, memory, peripherals, and programmable logic is made possible with a new bus architecture called the Configurable System Interconnect Bus (CSI). The Configurable System Interconnect Bus was specifically designed to facilitate re-use, guarantee timing, increase system throughput, and reduce system debug time in applications that require intense time-to-market and field upgrade View full abstract»

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  • A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process

    Page(s): 179 - 182
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    This paper describes the design of an FSK transmitter for the 433 MHz ISM (Industrial, Scientific, Medical) band, which is realized in a standard digital 0.5 μm CMOS technology. It includes the PA itself, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2 V supply and an output power reaching 10 dBm at 433 MHz View full abstract»

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  • Dynamic clock management for low power applications in FPGAs

    Page(s): 139 - 142
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    Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management View full abstract»

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  • A novel high-performance predictable circuit architecture for the deep sub-micron era

    Page(s): 503 - 506
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    Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger interwire capacitance which is responsible for large crosstalk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O2ABA), especially suited for the deep sub-micron regime. O 2ABA achieves reduction of crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O2ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages View full abstract»

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  • Finite-length signal quantization using discrete optimization

    Page(s): 455 - 458
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    This paper introduces a novel, discrete optimization based method for the computation of coarsely quantized, oversampled finite length digital signals. The method, while only suitable for offline computation, is more general than the established sigma-delta encoding technique, due to its capacity to take into account complex specifications and design trade-offs. Signal generation is formulated as a linearly constrained, convex, integer quadratic programming problem which is solved through an application specific branch-and-bound algorithm. The optimization method is illustrated with a fractional-N frequency synthesizer based modulator design example View full abstract»

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  • On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

    Page(s): 487 - 490
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    On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise View full abstract»

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  • On intellectual property protection

    Page(s): 517 - 523
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    New design paradigms based on the concept of system-on-chip are gradually replacing printed circuit board centric approaches. This trend is mainly due to two factors: far higher running speeds and greater miniaturization. The new paradigms will accelerate design cycles, which in turn will force designers to reuse existing and acquire new circuits ready to be integrated. Such acceleration will be possible only if highly specialized core authors, integrators, and foundries will be able to efficiently and safely exchange and handle their intellectual property, The field known as intellectual property protection is aimed at limiting all violations to intellectual property rights through appropriate design methodologies, tools, and infringement detection techniques. The paper surveys all published aspects of the intellectual properly protection problem, in the context of concerted VSIA efforts to define new standards and protocols View full abstract»

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  • A stand-alone integrated excitation/extraction system for analog BIST applications

    Page(s): 83 - 86
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    An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 μm CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks View full abstract»

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  • Low-power technique for on-chip memory using biased partitioning and access concentration

    Page(s): 275 - 278
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    In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different sizes of two sub-arrays by inserting transfer-gate into a bit-line. When a smaller array is accessed, the larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 codec LSI. Power consumption was reduced by 40% View full abstract»

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  • Effect of technology scaling on digital CMOS logic styles

    Page(s): 401 - 408
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    In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 μm CMOS technologies View full abstract»

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  • NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

    Page(s): 65 - 68
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    This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies View full abstract»

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