By Topic

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Date 24-24 May 2000

Filter Results

Displaying Results 1 - 25 of 131
  • Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

    Publication Year: 2000
    Save to Project icon | Request Permissions | PDF file iconPDF (1547 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 2000 , Page(s): 0_23 - 0_25
    Save to Project icon | Request Permissions | PDF file iconPDF (271 KB)  
    Freely Available from IEEE
  • Diagnosing resistive bridges using adaptive techniques

    Publication Year: 2000 , Page(s): 79 - 82
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    A systematic procedure for locating resistive bridges is presented. Critical path tracing is used to identify a set of “suspect” bridges whose presence could explain all of the observed faulty behavior of the circuit for the original test set. The set of suspects is then reduced by adaptively applying additional tests derived from the failing vector pairs in the original test set. Unlike other approaches, the approach presented here is not based on any bridge fault modeling and does not require any fault simulation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy

    Publication Year: 2000 , Page(s): 287 - 289
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    This paper describes the use of low cost, flash EEPROM switches to control redundancy in SRAM embedded memories. Flash cell design, operation and process technology are described. A 768K-bit embedded SRAM memory with flash controlled column redundancy and built in self-repair is presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process

    Publication Year: 2000 , Page(s): 5 - 8
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A ΔΣ ADC designed in a 0.6 μm CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 kΩ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fully-integrated low phase-noise nested-loop PLL for frequency synthesis

    Publication Year: 2000 , Page(s): 589 - 592
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    It is greatly beneficial to integrate the VCO. An efficient way to accomplish that is through the help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture that achieves very wide BW while maintaining the required frequency resolution and spur rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25 GHz bipolar process. The PLL achieves a phase-noise of -100 dBc/Hz at 10 kHz offset from 1 GHz and consumes 9.9 mA from a 3.3 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated capacitively coupled transformer and its application for RF IC's

    Publication Year: 2000 , Page(s): 349 - 352
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    This paper describes a low voltage topology that uses a passive element that is described as a “capacitively coupled transformer” (CCT). This structure can be easily implemented using an IC technology that supports both on chip MIM capacitors and high Q-inductors. The structure is used to design a low noise amplifier at 1.9 GHz. The LNA consumes 4 mA of current has a input IP3 of -4.5 dBm, a noise figure of 2.3 dB for a source resistance of 50 Ω, a minimum noise figure of 1.9 dB, and a gain of 10.1 dB. The topology maintains a high linearity without sacrificing noise figure and gain for a supply voltage of 1 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet

    Publication Year: 2000 , Page(s): 465 - 468
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 μm standard cell CMOS process for operation at 125 MHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings

    Publication Year: 2000 , Page(s): 357 - 360
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    This paper presents an active substrate noise suppression circuit using a pair of concentric guard rings. The outer guard ring senses the substrate noise, which is inverted and amplified by a SiGe circuit. This on-chip amplifier drives the inner guard ring such that efficient noise cancellation is achieved. A ring oscillator is used to sense the residual substrate noise. The measured noise suppression bandwidth is as high as 400 MHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

    Publication Year: 2000 , Page(s): 371 - 374
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85°C. The circuits were fabricated on a generic 0.5 μm digital CMOS process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architecture of cluster-based FPGAs with memory

    Publication Year: 2000 , Page(s): 131 - 134
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Direct digital frequency synthesis of low-jitter clocks

    Publication Year: 2000 , Page(s): 31 - 34
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The development of communication systems in the past years has increased the necessity to synthesize very accurate clocks. For example, in Digital Television (DTV) an audio data stream must be inserted into a video data stream, which implies that we must synchronize the audio clock with the video clock. According to one digital audio standard, the audio clock frequency is 5,6448 MHz, and with the PAL digital television standard, the video clock frequency is 35.46895 MHz. In this case, the division ratio is 112896/709379. Other division ratios are required with other DTV standards such as NTSC, SECAM or HDTV, and with other digital audio standard frequencies. Direct Digital Synthesis (DDS) is a popular technique that can be used to derive the audio frequency from the video frequency used as clock. A critical component of a DDS is its phase accumulator, which controls the DDS output frequency. The limited number of bits in the phase accumulator reduces its precision and its ability to express divide ratios defined with large integers. This will produce a phase error that accumulates with time to produce a low-band jitter in the output signal, which is particularly harmful when the output clock is used for synchronization purposes. This paper reviews some circuits found in the literature, which could be used to reduce the phase error given by a phase accumulator, and it presents a new phase correction technique which can give better results in terms of jitter, and which simplify design and implementation of practical DDS circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analog front-end LSI with on-chip isolator for V.90 56 kbps modems

    Publication Year: 2000 , Page(s): 327 - 330
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    This paper presents an isolated analog front-end (I-AFE) LSI with built-in isolation function for V.90, 56 kbps modems. The LSI has 1.5 kVrms. AC isolation and analog front-end functions within a 5 mm×4.5 mm die with 0.4 μm SOI CMOS process and a 50 pin TSOP package. The on-chip isolation approach eliminates external isolation devices such as transformers or photo-couplers. A 100 Mbps transmission rate is attained by the on-chip isolator View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A PN-acquisition ASIC for wireless CDMA systems

    Publication Year: 2000 , Page(s): 469 - 472
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    CDMA spread-spectrum systems require PN-acquisition to synchronize the transmitted signal at the receiver. Fast acquisition minimizes the amount of synchronization overhead required in the communication link for maximum system throughput. Yet, the fast acquisition should be done with low energy for portable applications. Conventional acquisition techniques using matched filters or serial correlators alone provide either fast pseudo-noise (PN) acquisition for CDMA or low power dissipation but not both. This paper presents an ASIC which implements a hybrid PN acquisition architecture that achieves both fast acquisition and up to 50% reduction in energy dissipation compared to conventional techniques. This ASIC has been fabricated using 0.5-μm CMOS technology with an area of 23 mm. It operates at 20 MHz with a 3.3 V supply and dissipates 50 mW per acquisition, or less than 1.5 mW per 50 byte packet View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Embedded DRAM: an element and circuit evaluation

    Publication Year: 2000 , Page(s): 291 - 294
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta2O5) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta2O5 equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta2 O5, and circuit topography View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design validation of .18 μm 1 GHz cache and register arrays

    Publication Year: 2000 , Page(s): 295 - 298
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 μm 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop

    Publication Year: 2000 , Page(s): 375 - 378
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A 900 MHz PLL frequency synthesizer implemented in 0.6 μm CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture

    Publication Year: 2000 , Page(s): 135 - 138
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the WarpTM 6.0 software View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO

    Publication Year: 2000 , Page(s): 577 - 580
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    A 2 V, 1 mA, 1.8 GHz to 2.45 GHz tuneable LC-tank CMOS VCO is presented. The tank is made of a MOS varactor (worked between accumulation and deep depletion) and a bondwire inductor, realized connecting two pads to a package frame lead, to be compatible with the production environment. This solution enables one to tune all components variations, while achieving the lowest phase noise times current consumption product, reported to date View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator

    Publication Year: 2000 , Page(s): 35 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of ΔΣ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-μm double-metal double-poly CMOS process, the chip occupies 2.28 mm2 and dissipates 3.7 mW with a supply voltage of 2 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS

    Publication Year: 2000 , Page(s): 333 - 340
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    During the nineties we have witnessed a string of advances in Silicon RF integration: from the introduction of the first integrated Si bipolar radios for GSM and DECT in the late eighties to the full single chip integration capabilities today using SiGe BiCMOS technologies. Where RF design used to be a black art, it is becoming a “normal practice” today View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving embedded software design and integration in SOCs

    Publication Year: 2000 , Page(s): 101 - 108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    The rapid advances in System-On-Chip (SOC) design enabled by improved process technology will be hindered unless major improvements are made in the specification, design and implementation of embedded software. Embedded software usually makes up at least half of the design content of an SOC device. In the future, it will constitute an even larger percentage of the design effort. In this paper we introduce a number of the major issues involved with design and integration of embedded software. We discuss some of the most recent standards, trends and capabilities that will provide effective solutions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

    Publication Year: 2000 , Page(s): 65 - 68
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell area overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low power high spectral purity frequency translational loop for wireless applications

    Publication Year: 2000 , Page(s): 593 - 596
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    PLLs with a mixer in the loop can perform the up-conversion function in communication systems which use constant envelope modulation techniques. These loops, usually named Frequency Translational Loops (FTL), perform the up-conversion of the modulated signal from an intermediate frequency to the transmitter frequency. Frequency translational loops used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase noise and spurious levels. This paper presents the design of a monolithic FTL which operates in the IF frequency range from 100 MHz to 450 MHz and the frequency range from 900 MHz to 1.9 GHz. The output phase noise level is -120 dBc/Hz at 400 kHz offset and 165 dBc/Hz at 20 MHz offset from a 900 MHz carrier and the spurious levels are lower than 60 dB below the carrier. These characteristics make the FTL suitable for use in cellular telephony applications such as GSM/DCS View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Finite-length signal quantization using discrete optimization

    Publication Year: 2000 , Page(s): 455 - 458
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    This paper introduces a novel, discrete optimization based method for the computation of coarsely quantized, oversampled finite length digital signals. The method, while only suitable for offline computation, is more general than the established sigma-delta encoding technique, due to its capacity to take into account complex specifications and design trade-offs. Signal generation is formulated as a linearly constrained, convex, integer quadratic programming problem which is solved through an application specific branch-and-bound algorithm. The optimization method is illustrated with a fractional-N frequency synthesizer based modulator design example View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.