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Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

Date 25-25 May 2000

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  • Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

    Publication Year: 2000
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000 , Page(s): 467 - 468
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    Freely Available from IEEE
  • MDD-based synthesis of multi-valued logic networks

    Publication Year: 2000 , Page(s): 41 - 46
    Cited by:  Papers (1)
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    A method for the synthesis of large Multi-Valued Logic Networks (MVLNs) using Multi-Valued Decision Diagrams (MDDs) is presented. The size of the resulting circuit is linear in the size of the original MDD. In contrast to previously presented approaches to circuit design using MDDs, here the nodes are not substituted by multiplexers. Instead, a small circuit is created representing the functionality of each edge in the graph. The resulting circuits have nice properties with respect to area/delay estimation and power dissipation. Experimental results are given to illustrate the efficiency of the approach View full abstract»

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  • Some properties of discrete interval truth valued logic

    Publication Year: 2000 , Page(s): 101 - 106
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    This paper focus on functions defined on a special subset of the power set of {0, 1, ..., r-1} (the elements in the subset will be called discrete interval truth values because they act precisely as intervals) and operations on. The truth values. The operations discussed in this paper will be called regular because they can be seen as an extension of the regularity which was introduced by Kleene in his ternary logic. M. Mukaidono investigated some properties of ternary functions which can be represented by the regular operations. He called such ternary functions “regular ternary logic functions”. Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states and/or initial stated in binary logic circuits that Boolean functions cannot cope with. They are also applicable to studied of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions to functions on the discrete interval truth values. Section 2 will give some of the basic definitions of discrete interval truth valued logic, and show dome of its mathematical properties. In Section 3 we will give logic formulas which represent minimum and maximum information loss functions View full abstract»

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  • On the intersection of maximal partial clones and the join of minimal partial clones

    Publication Year: 2000 , Page(s): 396 - 401
    Cited by:  Papers (4)
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    Let A be a nonsingleton finite set and M be a family of maximal partial clones with trivial intersection over A. What is the smallest possible cardinality of M? Dually, if F is a family of minimal partial clones whose join is the set of all partial functions on A, then what is the smallest possible cardinality of F? The purpose of this note is to present results related to these two problems View full abstract»

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  • Fast transforms for multiple-valued input binary output PLI logic

    Publication Year: 2000 , Page(s): 47 - 52
    Cited by:  Papers (2)
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    Fast forward and inverse transforms for multiple-valued input binary output PLI logic are derived. New matrix functions are introduced which allow feasible transformation of arbitrary q-valued input binary output functions. This allows representation of the function in the algebra of GF(2), where q⩾2. The representation of MVB functions in various functional bases having always fast algorithms is the foundation for the efficient synthesis of PLI expansions of MVB functions. The computational complexity of such algorithms is essentially reduced when compared to standard matrix multiplication and inversion based methods of the earlier work in PLI logic View full abstract»

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  • The synthesis of multiple-valued logic circuits using local-excitation-type neuron models

    Publication Year: 2000 , Page(s): 21 - 26
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    We propose a new neuron model to which local excitation phenomena in the organism are applied. We report some of the learning characteristics of the local-excitation-type neuron model in this paper. We have verified that the characteristics of the local-excitation-type neuron were changed by the learning method. Concerning the synthesis method of the 4-valued logic circuit, we note that the local-excitation-type neurons were used as an application example View full abstract»

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  • Propagation algorithm of behavior probability in power estimation based on multiple-valued logic

    Publication Year: 2000 , Page(s): 453 - 459
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    This paper analyses the propagation operations of signal's multiple-valued behavior while passing through the basic gates. Based on it the propagation algorithm of behavior probability is proposed. In comparison with the propagation algorithm of signal probability this algorithm have advantages that the calculation is direct one and the glitches resulted from race hazard can be taken into account, whereby the estimation accuracy of power dissipation can be improved View full abstract»

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  • Logic synthesis of controllers for B-ternary asynchronous systems

    Publication Year: 2000 , Page(s): 402 - 407
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    Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case. In this paper, a logic synthesis approach for designing the controller for a B-ternary data-path we have presented earlier is discussed. To control the B-ternary data-path asynchronously, external-binary, internal-ternary signaling is required. We derive an asynchronous state transition graph from the signal transition graph of the controller and then synthesize a hazard-free asynchronous implementation of the controller as a two-level combinational circuit together with a ternary-in binary-out C-element View full abstract»

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  • Computation of spectral information from logic netlists

    Publication Year: 2000 , Page(s): 53 - 58
    Cited by:  Papers (1)
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    Spectral information can be used for many CAD system tasks including synthesis, verification and test vector generation. We analyze the problem of extracting spectral information from Boolean and multi-valued logic netlists. It is shown that spectral information may be calculated directly from output probabilities and a method for extracting output probabilities from general graphs is described. As a special case, we consider AND/OR graphs which are a data structure recently proposed as an alternative to decision diagrams. Experimental results are given to demonstrate the efficiency of our approach View full abstract»

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  • Implementation of multiple-valued multiplier on GF(3m) using current mode CMOS

    Publication Year: 2000 , Page(s): 221 - 226
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    The multiplication algorithm of two polynomials on finite fields GF(3m) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(33) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 μm standard CMOS device parameters, 20 μA unit current level and 3.3 V VDD voltage supply View full abstract»

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  • On the number of dependent variables for incompletely specified multiple-valued functions

    Publication Year: 2000 , Page(s): 91 - 97
    Cited by:  Papers (6)
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    This paper considers the minimization of dependent variables in functions with many don't cares. It also derives the conditions for almost all randomly generated function to be redundant in at least one variable. Experimental results support the validity of the approach View full abstract»

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  • Fuzzy decision diagrams for the representation, analysis and optimization of rule bases

    Publication Year: 2000 , Page(s): 127 - 132
    Cited by:  Papers (2)
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    When no expert knowledge is available, fuzzy if-then rules may be extracted from examples of performance of a system. For this, an a priori decision on the number of linguistic terms of the linguistic variables may be required. This may induce a “rigid granularity”, usually finer than that actually required by the system. Fuzzy Decision Diagrams are introduced as an efficient data structure to represent fuzzy rule bases and to systematically check their completeness and consistency. Moreover if the hypothesis of rigid granularity holds, reordering of the variables of a Fuzzy Decision Diagram may lead to a compacter and more precise rule base. The concept of reconvergent subgraphs is introduced to support the search for effective reorderings View full abstract»

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  • High-radix parallel VLSI dividers without using quotient digit selection tables

    Publication Year: 2000 , Page(s): 345 - 352
    Cited by:  Papers (6)
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    This paper presents the design and evaluation of high-radix parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with less hardware complexity, in comparison with the binary counterparts. This paper also presents the experimental fabrication of the radix-4 divider in 0.35 μm CMOS technology View full abstract»

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  • Chaining techniques for automated theorem proving in many-valued logics

    Publication Year: 2000 , Page(s): 337 - 344
    Cited by:  Papers (4)
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    We apply chaining techniques to automated theorem proving in many-valued logics. In particular, we show that superposition specializes to a refined version of the many-valued resolution rules introduced by Baaz and Fermuller, and that ordered chaining can be specialized to a refutationally complete inference system for regular clauses View full abstract»

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  • Data mining of weak functional decompositions

    Publication Year: 2000 , Page(s): 77 - 82
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    A weak decomposition of an incompletely specified function f is a decomposition of some completion of f. Using a graph-theoretical characterization of functions that admit such decompositions, we present a technique derived from the a priori algorithm that allows a data mining approach to identifying these decompositions View full abstract»

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  • Gray scale image compression based on multiple-valued input binary functions, Walsh and Reed-Muller spectra

    Publication Year: 2000 , Page(s): 279 - 284
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    A new method for the lossless compression of gray scale images has been proposed. Coding of intensities is first applied to make the data more amenable for compression. A prediction process is performed followed by the mapping of prediction residuals. The prediction residuals are then split into bit planes to which the compression technique is applied. These bit planes can be coded as uncompressed, expressed as minterms or compressed using a variable block-size segmentation and coding. A dictionary of patterns is formed from simple multiple-valued input binary functions, basic Walsh, triangular Reed-Muller weights and some frequently occurring patterns. Other compression methods used in our scheme include minterm coding, coordinate data coding, Generalized k-Variable Mixed-Polarity Reed-Muller expansion and the reference row technique. The proposed scheme has been implemented in the C language and compared with other stare-of-the-art techniques View full abstract»

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  • Silicon single-electron devices and their applications

    Publication Year: 2000 , Page(s): 411 - 420
    Cited by:  Papers (9)
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    We have developed two novel methods of fabricating very small Si single-electron transistors (SETs), called PAttern-Dependent OXidation (PADOX) and Vertical PAttern-Dependent OXidation (V-PADOX). These methods exploit special phenomena that occur when small Si structures on SiO2 are thermally oxidized. Since the size of the resultant Si island of the SET is about 10 nm, we can observe the conductance oscillations in the SET even at room temperature. The controllability and reproducibility of these methods are excellent because of the stability of the thermal oxidation process. We are using PADOX and V-PADOX to integrate single-electron devices (SEDs)for sophisticated functions. We have fabricated and tested several kinds of memory and logic devices, This paper also describes applications of multi-input gate SETs to multiple-valued logic circuits View full abstract»

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  • Implementation of multiple-output functions using PQMDDs

    Publication Year: 2000 , Page(s): 199 - 205
    Cited by:  Papers (2)
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    A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (shared reduced ordered Binary Decision Diagrams). In this paper, we propose PQMDD (Paged Quasi-reduced ordered Multi-valued Decision Diagram) as a new data structure. A function is represented by a PQMDD, and stored in memory. Dedicated control circuits traverse the PQMDD in parallel. We represent multiple-output function for benchmark functions by SBDDs and PQMDDs and compare the size of memory and computation time View full abstract»

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  • An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access

    Publication Year: 2000 , Page(s): 430 - 437
    Cited by:  Papers (2)
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    This paper investigates a multiple-valued code-division multiple access (MV-CDMA) technique to achieve efficient data transmission and processing in VLSI systems. CDMA employs a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier. Orthogonal property of m-sequences enables us to multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission. With reduced interconnection. Also, randomness of m-sequences offers the high tolerance to noise interference. In the case of conventional CDMA, however, co-channel interference due to carrier phase offset error severely restricts the available number of multiplexing. In order to eliminate carrier phase offset error, we propose a new class of multiple-valued m-sequences. An application example of neural networks is discussed to demonstrate the feasibility of MV-CDMA in terms of reducing interconnections and eliminating co-channel interference View full abstract»

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  • Multi-valued sub-function encoding in functional decomposition based on information relationships measures

    Publication Year: 2000 , Page(s): 83 - 90
    Cited by:  Papers (2)
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    Functional decomposition is becoming more and more popular, because it is more general than all other known logic synthesis approaches and it seems to be the most effective approach for LUT-based FPGAs, (C)PLDs and complex CMOS-gates. The multi-level functional decomposition can be seen as a recursive splitting of a given function, into two sub-functions: the predecessor (bound-set) function and successor function, initially, the bound set function is a multi-valued (symbolic) function, where a certain value (symbol) is assigned to each particular input-cube compatibility class of the function being decomposed. To be implemented with binary logic, the multi-valued bound-set function must be expressed as a set of binary functions. This transformation is called the multi-valued sub-function encoding. It can be performed by the binary code assignment to each particular input-cube compatibility class. It determines the resulting binary predecessor and successor sub-functions and therefore influences the quality of the resulting circuit to a high degree. In this paper, a new method of the multi-valued sub-function encoding is presented. The method is based on the information relationship measures. Experimental results from the prototype CAD-tool that implements the method demonstrate that it is able to efficiently construct extremely effective circuits for symmetric functions. Results for asymmetric functions are also very good View full abstract»

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  • Independence of the axioms of Boolean algebra in multiple-valued logic

    Publication Year: 2000 , Page(s): 107 - 112
    Cited by:  Papers (3)
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    We apply the Method of Indeterminate Coefficients to examine independence of some sets of axioms of Boolean algebra and to list up some candidates of independent and complete sets of axioms of Boolean algebra. And we prove for some of these candidates that they are in fact independent and complete View full abstract»

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  • DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage

    Publication Year: 2000 , Page(s): 423 - 429
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    A multiple-valued logic-in-memory VLSI with fast reprogrammability is proposed to realize transfer-bottleneck-free VLSI systems. A basic component, in which a dynamic storage function and a multiple-valued threshold-literal function are merged, can be simply implemented by charge addition and charge storage with a DRAM-cell-based circuit structure. Any logic circuits with multiple-valued inputs and binary outputs can be realized by the combination of the basic components and logic-value conversion. As a typical example, a fully parallel magnitude comparator between three-valued input and stored words is designed by using the proposed logic-in-memory VLSI architecture. Its performance is superior to that of a corresponding binary implementation by using HSPICE simulation under a 0.5-μm CMOS technology View full abstract»

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  • Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic

    Publication Year: 2000 , Page(s): 438 - 443
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    A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, is proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, it is demonstrated that the effective chip area of the proposed four-valued current-mode full adder is reduced to 5% under the same switching speed in comparison with the corresponding binary CMOS implementation View full abstract»

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  • Novel resonant-tunneling multiple-threshold logic circuit based on switching sequence detection

    Publication Year: 2000 , Page(s): 317 - 322
    Cited by:  Papers (1)
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    We present a novel multiple-threshold circuit using resonant-tunneling diodes (RTDs). The logic operation is based on detecting a switching sequence in the RTD circuit. This scheme enables us to increase the number of threshold voltages by more than a factor of two compared with previous RTD-based MVL circuits. SPICE simulation shows that the circuit can operate at a clock frequency as high as 10 GHz. A 4-bit flash analog-to-digital converter, which uses the present circuit as a quantizer, is also discussed View full abstract»

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