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High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), 2013 IEEE 10th International Conference on

Date 13-15 Nov. 2013

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  • [Front cover]

    Page(s): C4
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - xxxii
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  • HPCC 2013: Message from General Chairs

    Page(s): xxxiii
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  • HPCC 2013: Message from Program Chairs

    Page(s): xxxiv
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  • HPCC 2013: Message from Workshop Chairs

    Page(s): xxxv
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  • HPCC 2013: Message from Steering Chairs

    Page(s): xxxvi
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  • HPCC 2013: Organizing and Program Committees

    Page(s): xxxvii - lxiii
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  • EUC 2013: Message from General Chairs

    Page(s): lxiv
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  • EUC 2013: Message from Program Chairs

    Page(s): lxv
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  • EUC 2013: Message from Workshop Chairs

    Page(s): lxvi
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  • EUC 2013: Message from Steering Chairs

    Page(s): lxvii
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  • EUC 2013: Organizing and Program Committees

    Page(s): lxviii - lxxxiii
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  • TSP 2013: Message from Workshop Chairs

    Page(s): lxxxiv
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  • IntelNet 2013: Message from Workshop Chairs

    Page(s): lxxxv
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  • EMCA 2013: Message from Workshop Chairs

    Page(s): lxxxvi
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  • HPTC 2013: Message from Workshop Chairs

    Page(s): lxxxvii
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  • NOPE 2013: Message from Workshop Chairs

    Page(s): lxxxviii
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  • DMIoT 2013: Message from Workshop Chairs

    Page(s): lxxxix
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  • Phase Based and Application Based Dynamic Encoding Scheme for Multi-level Cell STT-RAM

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (798 KB) |  | HTML iconHTML  

    The emerging Spin Torque Transfer memory (STT-RAM) appeared to be a promising candidate for future on-chip caches because of its high storage density, zero leakage power consumption, long endurance, high access speed etc. However, before the STT-RAM can be deployed in on-chip caches, there is one critical issue that has to be solved: the high write current of STT-RAM, which results in high dynamic power consumption. Each cell of multi-level cell STT-RAM (MLC STT-RAM) has four resistance states which can present the four 2-bit logical value pairs (00, 01, 10 and 11). We find that the proportion of the 2-bit logical value pairs written to L2 Cache changes with time and applications. Since the four resistance states have different write energies, we therefore propose schemes to map the four resistance states to the four 2-bit logical value pairs dynamically according to their proportions. The resistance state which has lower write energy can represent the 2-bit logical value pair which appears more frequently. In this paper, we propose phase based dynamic encoding policy (PBDE) and application based dynamic encoding policy (ABDE). The PBDE divides an entire process into many phases, and each phase chooses its best encoding policy to minimize power consumption. The ABDE chooses the best encoding scheme for cache blocks according to application types. Our evaluations show that PBDE and ABDE can achieve 2.7% and 4.5% write energy reduction over STT-RAM based caches respectively. View full abstract»

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  • SPD-RAID4: Splitting Parity Disk for RAID4 Structured Parallel SSD Arrays

    Page(s): 9 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    Data-intensive applications like video processing and bioinformatics increasingly demand a high-performance and highly reliable storage system. Hard disk drive (HDD) has long been used as a standard storage device for most existing storage systems. Recently, NAND-flash memory based solid state drives (SSDs) are gradually exploited to replace HDDs in enterprise computing infrastructures due to their salient features such as high performance, low power consumption, and excellent shock-resistance. With rapid price decreasing and capacity increasing, flash SSD based disk arrays organized in some RAID structures become feasible and greatly needed. In this paper, we propose a new RAID4 architecture called SPD-RAID4 (Splitting Parity Disk - RAID4) for parallel SSD arrays. It splits the parity disk of a traditional RAID 4 array into configurable number of smaller ones. Thus, multiple small parity SSDs operate in tandem with data SSDs to achieve a high performance and high level of reliability. We compare the performance of SPD-RAID4 with conventional RAID4 and RAID5 architectures by using both real-world traces and synthetic benchmarks. Experimental results demonstrate that in terms of mean response time SPD-RAID4 outperforms standard RAID5 structured SSD arrays by up to 20.3%. Compared with standard RAID4, SPD-RAID4 achieves a performance gain up to 40.6%. View full abstract»

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  • StackPool: A High-Performance Scalable Network Architecture on Multi-core Servers

    Page(s): 17 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2547 KB) |  | HTML iconHTML  

    There are numerous proprietary appliances in operators' networks. These appliances consume a lot of electricity and plenty of space to deploy, which lead to high operating expense (OPEX) for operators. Network Function Virtualisation (NFV) is introduced to solve this problem. NFV consolidates many network devices into network applications, which can be running on industry commodity servers. Those appliances are different from routers, because they have to handle protocol processing above network layer and provide socket APIs to various applications, which need full protocol stack support instead of packet forwarding only. Unfortunately, despite increasingly high speed bandwidth up to 10 Gbps or even 40 Gbps on commodity multi-core servers, network protocol processing bottlenecks are identified, such as throughput does not scale by the number of cores, or stack processing latency is too long for some applications, etc. In this paper, the reasons for poor stack performance (especially performance scalability and stack process latency) in software are systematically analyzed. And based on improving such analysis results, we propose Stack Pool, a novel high-performance scalable network architecture on multi-core servers. Stack Pool is constituted by multiple isolated virtual lanes. Each virtual lane contains an independent protocol stack instance, several pairs of hardware queues in NICs, as well as socket instances located in the stack instance. Each logical CPU core is responsible to process packets in a virtual lane. Flow director in NIC and lane selector in Stack Pool direct packets of different flows to several virtual lanes based on packet headers. We have implemented a Stack Pool prototype to show that the approach is promising. The Stack Pool outperforms standard Linux protocol stack with approximately 7 times throughput of UDP or 3 times that of TCP in a single virtual lane. Moreover, Stack Pool performance accrues linearly when scale to multiple cores, e.g.,- 10.7 and 17.2 times on 6 cores of UDP transmit and receive respectively, and 6.5 times of TCP throughput on 6 logical cores. At the same time, packet latency on Stack Pool is approximated only 1/4 than that on native Linux stack. View full abstract»

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  • QoSFM: QoS Support for Metadata I/O in Parallel File Systems

    Page(s): 29 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (739 KB) |  | HTML iconHTML  

    Large parallel file systems (PFSs) must service multiple independent workloads concurrently. Workloads often require different quality of service (QoS) of metadata I/O. However, existing PFSs are unable to differentiate metadata I/O from different workloads. There are many researches on QoS support of storage system, they do not focus on metadata I/O of PFSs as one metadata I/O can have several sub-operations and different sub-operations have different access size. In addition, users cannot specify metadata QoS requirements without a suitable QoS specification. This paper presents a novel scheme QoSFM (QoS Support for Metadata) to support metadata I/O QoS in PFSs. QoSFM allows users to specify workloads' metadata QoS requirements through our two-layered QoS specification mechanism. QoSFM can dynamically translate the workload-level goals into system resource needs such as service time per time window and sub-operation latency. Client-side controllers throttle the metadata I/O based on service time allocation to meet the throughput goal while metadata servers (MDSs) reorder the sub-operations based on deadlines to meet the latency goal. Extensive simulations show that QoSFM can effectively satisfy workload-level metadata I/O QoS requirements. Meanwhile, results also show that QoSFM has low overhead. View full abstract»

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