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VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on

Date 28-30 April 2014

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Displaying Results 1 - 25 of 82
  • Skillfully diminishing antenna effect in layer assignment stage

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest. View full abstract»

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  • Triangle-based process hotspot classification with dummification in EUVL

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (563 KB) |  | HTML iconHTML  

    As technology node advances, Extreme Ultraviolet Lithography (EUVL) is regarded as the most promising technology for improving the lithographic printability. However, there are still several challenges in EUVL like the most critical flare effect that causes patterning distortions. As a result, dummy fills are added to a layout (i.e., dummification) to compensate the flare effect. Although dummy fills are used to alleviate the flare effect, process hotspots still cannot be fully eliminated and are essential to be detected in the early design stages. Pattern matching is one of the most popular and widely-used technique to detect the process hotspots. However, existing pattern-matching-based algorithms may not effectively detect all process hotspots under the consideration of dummification. In this paper, we propose a two-stage triangle-based algorithm for process hotspot classification while considering the impact of dummification in EUVL. Experimental results show that our proposed algorithm is very effective and efficient compared with the state-of-the-art process hotspot classification algorithm. View full abstract»

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  • Two-staged parallel layer-aware partitioning for 3D designs

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1667 KB) |  | HTML iconHTML  

    As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods. View full abstract»

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  • Keep-Out-Zone analysis for three-dimensional ICs

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB) |  | HTML iconHTML  

    One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC. View full abstract»

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  • A 360-degree panoramic video system design

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system. View full abstract»

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  • A novel abstraction-guided simulation approach using posterior probabilities for verification

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (657 KB) |  | HTML iconHTML  

    This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance as well as allow the simulation to deal with multiple target states at a time. Experimental results show that the simulation using posterior probabilities as guidance is much more efficient than that using the abstract distances, and the multiple target states simulation framework reduces the simulation cycles effectively. View full abstract»

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  • Output selection for test response compaction based on multiple counters

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2661 KB) |  | HTML iconHTML  

    Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead. View full abstract»

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  • On efficient error-tolerability evaluation and maximization for image processing applications

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1198 KB) |  | HTML iconHTML  

    With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs. View full abstract»

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  • Oscillation-based diagnosis by using harmonics analysis on analog filters

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (749 KB) |  | HTML iconHTML  

    The Oscillation-Based Test (OBT) method converts the circuits under test (CUTs) into self-oscillating mode by changing CUT's typology or adding feedback path(s). In traditional OBT, the frequencies and amplitudes of sinusoidal oscillation are used as fault features to build up the fault dictionary, which is capable of test but not diagnosis. This paper designs harmonic feedback path to enlarge the harmonics in oscillation, and then builds up fault dictionary to diagnose the analog faults and eliminate the deviation effects by membership functions. The simulation and PCB experiment results prove that the proposed method is both applicable and practical. View full abstract»

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  • An FPGA implementation of high-throughput key-value store using Bloom filter

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (765 KB) |  | HTML iconHTML  

    This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. Experimental results show significant performance improvement over existing approaches. View full abstract»

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  • SAT-based complete logic implication with application to logic optimization

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    Logic implication that finds necessary assignments for a given set of value assignments in a Boolean circuit has a wide set of applications in the computer-aided design field, such as logic optimization, design verification, and test pattern generation. Due to the high computational complexity, earlier methods either cannot or do not find all necessary assignments, limiting their qualities in the applications. With the dramatic advance of Boolean satisfiability (SAT) solving techniques, applying the efficient SAT solving techniques to logic implication seems promising. Thus, the paper presents a SAT-based method for complete logic implication. Given a set of value assignments, it first simulates a large number of random patterns and collects a set of candidate necessary assignments based on the simulation results. Then, instead of validating each candidate one by one, it iteratively calls a SAT solver to identify the invalid candidates and remove them. At each SAT solving iteration, at least one invalid candidate can be removed. Finally, only the valid candidates are left and they are exactly all the necessary assignments. Furthermore, we extend the method to compute all mandatory assignments for a stuck-at fault test and apply the extended method to enhance a logic optimization algorithm whose quality largely depends on the completeness of the mandatory assignment computation. The experimental results show that the enhanced method achieves an average of 1.3× improvement in circuit size reduction with acceptable CPU time overhead. View full abstract»

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  • Simultaneous optimization for low dropout regulator and its error amplifier with process variation

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2753 KB) |  | HTML iconHTML  

    Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The process variation effects are also considered in this work to guarantee the circuit performance after manufactured. As demonstrated in the experiments, the proposed approach successfully solves the unreachable specification in previous work and significantly improves the design yield of the generated circuits. View full abstract»

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  • An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (681 KB) |  | HTML iconHTML  

    This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications. View full abstract»

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  • Full system simulation framework for integrated CPU/GPU architecture

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction. In this paper, we develop the first cycle-level full-system simulation framework for CPU-GPU integration with detailed memory models. With the simulation framework, we analyze the communication cost between the CPU and GPU for GPU workloads, and perform memory system characterization running both applications concurrently. View full abstract»

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  • Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (765 KB) |  | HTML iconHTML  

    This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design. View full abstract»

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  • A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (666 KB) |  | HTML iconHTML  

    PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at early physical implementation stages. They are rarely relevant after the routing stage when few routing resources are left and hence call for a repair strategy. The reason is that the traditional methods often apply wire widening or wire density increment directly without taking signal routing into account. Moreover, intuitively adding connections to the PDNs using the entire space available is quite time-consuming and eventually leads to lack of routing resources for later design ECO. Therefore, in this paper, we propose an approach to efficiently repairing the PDNs at the signoff stage. The greedy-Pareto-optimal (GPO) method is used to select the most effective regions to enhance the power rail connectivity. Maximizing the IR-drop improvement and minimizing the use of routing resources are considered at the same time. The method has been incorporated in our backend design flow and verified by leveraging a commercial P&R tool. On a test case of image signal processor, the experimental results show that the proposed PDN ECO approach can improve the worst IR-drop from 9.34% to 3.84% (i.e., 58.9% improvement) in the post-routing stage, where the ECO wire pitch is 3.5 times the minimal routing pitch. View full abstract»

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  • A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense. View full abstract»

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  • Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented, integrated, and tested. To prove the compliance with ISO 26262 hardware development process, quantitative evaluations on the hardware are indispensable. These quantitative evaluations are known as hardware architecture metrics and probabilistic hardware metrics. The assessment results qualify a design with an automotive safety integrity level (ASIL) which ranges from ASIL-A (lowest) to ASIL-D (highest). In this paper, we implemented an exemplary safety microprocessor to demonstrate the ISO 26262 hardware assessment process. The derivation procedures of the ASIL level from the hardware architecture metrics and probabilistic hardware metrics are fully discussed. Based on the evaluation results, we also provide design suggestions for the ISO 26262 safety hardware design. View full abstract»

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  • Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of failed area ratio (FAR). View full abstract»

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  • Efficient test length reduction techniques for interposer-based 2.5D ICs

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1637 KB) |  | HTML iconHTML  

    Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to investigate the efficient post-bond test technique for the 2.5D ICs with silicon interposer. In order to efficiently reuse the functional interconnects as the parallel TAM (test access mechanism) for testing dies, a novel macro-die-based interconnect reuse strategy and its corresponding design-for-test (DFT) architecture are proposed in this paper. The proposed strategy merges several dies to form a macro die and then connected to other dies to form a daisy chain for testing. Experimental results show that the proposed techniques have higher success rates for the required TAM width constraints. Moreover, since we can get wider TAMs, the test length then can be reduced significantly. View full abstract»

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  • A novel DFT architecture for 3DIC test, diagnosis and repair

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (849 KB) |  | HTML iconHTML  

    Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as double TSVs & double μ-bumps schemes. In this paper a novel DFT technique is presented based on the double resource schemes. Challenges to two-die, multi-tier, and numerous interconnects are handled by proposed testable, diag-nosable, repairable, and scalable element, structure, and flow. View full abstract»

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  • A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (729 KB) |  | HTML iconHTML  

    A 1.5 GHz all-digital fractional-N frequency-locked loop by utilizing a ΔΣ frequency-to-digital converter (FDC) is implemented in 0.18 μm CMOS. Different from the conventional all-digital phase-locked loop, the all-digital frequency-locked loop (ADFLL) with a 1-bit ΔΣ frequency detector (FD) avoids complex time-to-digital converter (TDC) design and achieves a fine frequency resolution with bi-level oversampled frequency detection, thus enabling low-cost high-frequency synthesis without requiring an advanced CMOS technology. A finite impulse response (FIR) filter is designed to reduce quantization noise from the ΔΣ FDC and provides highly linear loop dynamics in the type-I feedback system. Experimental results show that the proposed ADFLL at 1.4 GHz output achieves a phase noise of -118 dBc/Hz at a 1 MHz offset frequency, consuming 7.3 mW from a 1.8 V supply. View full abstract»

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  • A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (675 KB) |  | HTML iconHTML  

    A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage. View full abstract»

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  • A low-area digitalized channel selection filter for DSRC system

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1013 KB) |  | HTML iconHTML  

    This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged form 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 40±2.5MHz. The input third-order intercept point is 6dbm. View full abstract»

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  • Design of low-cost elliptic curve cryptographic engines for ubiquitous security

    Publication Year: 2014 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (593 KB) |  | HTML iconHTML  

    This paper presents Elliptic Curve Cryptographic (ECC) engines for very constrained devices in ubiquitous security such as passive RFID tags. The proposed scheduling of atomic operations optimizes the EC scalar multiplication at a higher level of finite field arithmetic with improved resource arrangement. Our architecture of arithmetic unit (AU) and circular-shift-based register file (RF) realizes the scheduling effectively. Using 65nm process technology, the ECC engine can produce one scalar multiplication in 250ms with 10.5K gates. The area overhead is 1.23× to 1.54× smaller than other designs; the power of 4.68μW and energy of 1.17μJ is also the lowest. The comparison shows that our ECC engines outperform others in terms of cycles, area, power and energy. View full abstract»

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