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VLSI Test Symposium (VTS), 2014 IEEE 32nd

Date 13-17 April 2014

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  • [Copyright notice]

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  • [Blank page]

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  • [Title page]

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  • [Copyright notice]

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  • Foreword

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  • Organizing committee

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  • Steering and program committees

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  • Acknowledgments

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  • VTS 2013 Best Paper Award [includes 2 other awards]

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  • TTTC: Test technology technical council

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  • Fault simulation with test switching for static test compaction

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    Static test compaction procedures reduce the number of tests in a given test set without reducing the fault coverage. Static test compaction procedures can use the set or the number of faults detected by each test as guidance. Fault simulation without or with limited fault dropping is needed for producing this information. However, it can be time consuming. To compute the information needed for guiding static test compaction efficiently, this paper describes a fault simulation procedure with fault dropping that attempts to balance the sizes of the sets of detected faults. This is achieved by switching the test being simulated as soon as it detects a fault. Differences in the numbers of detected faults, in spite of the attempt to balance them, is attributed to the relative effectiveness of the tests in detecting target faults. The paper shows that reordering a test set based on the results of fault simulation with test switching is effective when applied prior to forward-looking reverse order fault simulation. In general, the procedure can be used in applications where it is advantageous to balance the sets of detected faults. View full abstract»

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  • Fast evaluation of test vector sets using a simulation-based statistical metric

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate the time when the fault coverage saturates. This is done with only one pass of simulation and it provides a measure of the effectiveness of the test sequence when applied to the circuit-under-test; additionally, the fault coverage can be estimated with a relatively small number of test vectors. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks, and a RISC processor (OR1200), show an average error of 2.85% in the estimated fault coverage compared with the fault coverage from full fault simulation, with an average speedup over 8× for large circuits. View full abstract»

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  • Improving CMOS open defect coverage using hazard activated tests

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic values through the charging of the floating node by small leakage currents in the circuit, although with large delays. It is well known that many open defects are not covered by commonly employed TDF launch on capture (LOC) scan delay tests; the coverage of specially generated transistor stuck-open tests published in the literature is only modestly better. It is commonly assumed that such undetected open faults are benign because the circuit states needed to activate them cannot be reached in normal functional operation. However, traditional test generation only considers final “steady state” signal values and ignores transients. In practice CMOS circuits experience many more transient states from the large number of hazards that occur during switching transitions. Many undetected open defects can be activated by such hazards during normal operation and cause a functional error. Such open faults must be detected by tests targeting low DPPMs. In this paper we present an ATPG based delay test methodology to target a key class of such hazard activated open faults that are not detected by traditional stuck open tests. Through detailed SPICE simulations, we show that the detected open defects can in fact be activated by such tests and therefore result in erroneous outputs in normal functional operation. View full abstract»

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  • Efficient Monte Carlo-based analog parametric fault modelling

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1464 KB) |  | HTML iconHTML  

    The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to measure datasheet specifications. The lack of a comprehensive fault model that is computationally efficient makes the elimination of any tests or the use of lower-cost alternative tests too risky or too time-consuming. Monte Carlo simulations offer a general way to model parametric variations, but inherently focus on normal instead of defective performance. This paper defines a new, general fault model comprising a set of marginally failing circuit instances to evaluate parametric fault coverage of test suites in a way that reduces the number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the technique is applied to six parameters of an RF low-noise amplifier (LNA). View full abstract»

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  • A method for phase noise extraction from data communication

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Evaluating the phase noise of a data stream may be accomplished with the Fast Fourier Transform (FFT) of the signal, if the resolution is high enough, or captured using a mixer and local oscillator. To eliminate these requirements, we present a method for capturing phase noise amplitude from arbitrary bit stream data using a Time to Digital Converter. View full abstract»

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  • Accurate and efficient method of jitter and noise separation and its application to ADC testing

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    Jitter is a crucial factor in high speed and high performance ADC testing. This paper proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics does not need to know before the processing. The algorithm is robust enough that non-harmonic spurs does not affect the estimation result. Using the proposed algorithm, specifications of SNR and ENOB of the ADC under test can be obtained without jitter effect. Simulation results of ADCs with different resolutions show the functionality and accuracy of the method. View full abstract»

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  • Innovative practices session 1C: Existing/emerging low power techniques

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (105 KB) |  | HTML iconHTML  

    Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis. View full abstract»

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  • Testing methods for a write-assist disturbance-free dual-port SRAM

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new write-assist dual-port SRAM proposed in [10] by using a 28nm LP process and then discussed the faulty behavior of injecting different resistive-open defects into both the SRAM cell and write-assist circuit. Next, we developed new test methods to detect the hard-to-detect resistive-open defects and proposed a corresponding March-like algorithm that covers a widely used March C- as well as the proposed test methods. Last, the required DfT for the proposed test methods was also discussed. View full abstract»

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  • Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (489 KB) |  | HTML iconHTML  

    In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodology consists of two test procedures. First, faulty cells suffering from wearout mechanisms in the SRAM system are isolated. Then, these faulty cells are tested to determine the cause of wearout. View full abstract»

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  • Fault modeling and test algorithm creation strategy for FinFET-based memories

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1065 KB) |  | HTML iconHTML  

    FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs. View full abstract»

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  • New topic session 2B: Co-design and reliability of power electronic modules — Current status and future challenges

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB) |  | HTML iconHTML  

    Power electronics covers various disciplines, especially semiconductor, circuit design, thermal design (heat transfer, fluid flow), electromagnetics (EMI, Inductors, transformers), digital electronics, control theory, and materials science in the context of packaging and reliability engineering. It also covers a wide range of power (mW to MW), temperature (−55C to 275C), frequencies (DC to GHz) and dimensions (um to km). The global power electronics market is worth over $200Bn and is seeing significant growth in sectors such as aerospace, automotive and energy generation, transmission and distribution. This presentation will discuss the current status and future challenges in the design of power electronics components and systems. In particular co-design in terms of the modeling and analysis toolsets that enable power electronics designers to undertake thermal, electromagnetic and mechanical analysis of new power electronics components and systems, as well as the need for an holistic approach to designing such systems from the devices to convertors and drives in an integrated manner. View full abstract»

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  • Innovative practices session 2C: Advanced in yield learning

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB) |  | HTML iconHTML  

    The onset of FinFET technology nodes brings with it additional challenges in ramping yields due to new defect behaviors and new hardships in the physical failure analysis process. This presentation highlights these challenges and makes the argument that improved scan based diagnosis capabilities that leverage a transistor level understanding of the cells will be necessary to combat these challenges. View full abstract»

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  • A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (945 KB) |  | HTML iconHTML  

    One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the inductor also enables continuous, lossless average load current sensing of the DC-DC converter across the inductor. Both the BIST circuit and the primary signal chain utilize low analog complexity frequency-domain ΔΣADC. The ΔΣADC decimation filter nulls also provide current ripple cancellation and average current extraction. The BIST module can measure filter inductance values ranging from 3.6μH to 22.3μH range with average 2.0% error and inductor DCR 13mΩto 68mΩ range with average 2.1% error. The average current sensing enabled by the BIST technique achieves current measurement accuracy with average 2.3% error for 0.1A-1A range load current. BIST and current sensing modules occupy less than 6% of total chip area. The BIST circuitry is fabricated and tested with a 12V input, 1V-11.5V output range, for a 3W output power digital DC-DC converter. View full abstract»

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  • Alternative “safe” test of hysteretic power converters

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (849 KB) |  | HTML iconHTML  

    This paper presents a novel alternative “safe” test method for line and load regulation specifications of hysteretic controlled switching power converters. These specifications have not been tested in production before because the conventional measurement techniques lead to huge voltage spikes during switching transients. Those voltage spikes are caused by energy accumulation from parasitic inductances of ATE interface board to input capacitance of the device under test (DUT) and can damage DUT's internal circuitries. The proposed alternative test approach offers a “safe” manufacturing test of load/line regulation specifications of hysteretic controlled switching power converters through a carefully altered feedback circuit and a current-limited load. Through injecting the altered feedback circuit with a carefully crafted stimulus, the load and line regulation specifications of DUT are accurately predicted. This test approach is facilitated by the use of a DAC for stimulus generation and ADC for DUT response capturing. Both simulated data and hardware measurements are used to demonstrate the viability of the proposed ”safe”testing method. View full abstract»

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  • Accelerating capture of infrequent errors on ATE for silicon TV tuners

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    Infrequent errors, such as unwanted glitches occurring once every a few seconds in silicon tuners, are very costly to capture in production due to long test time by the nature of the errors. The paper presents a novel scheme that reduces the test time from a few seconds to a few tens milliseconds. The scheme has been implemented to test millions of silicon TV tuners, and field defects caused by the glitches were successfully eliminated. View full abstract»

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