By Topic

2014 IEEE 32nd VLSI Test Symposium (VTS)

Date 13-17 April 2014

Filter Results

Displaying Results 1 - 25 of 76
  • [Copyright notice]

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (21 KB)
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • [Title page]

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (58 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (58 KB)
    Freely Available from IEEE
  • Foreword

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (58 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing committee

    Publication Year: 2014, Page(s):1 - 3
    Request permission for commercial reuse | PDF file iconPDF (468 KB)
    Freely Available from IEEE
  • Steering and program committees

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (49 KB)
    Freely Available from IEEE
  • Acknowledgments

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (49 KB)
    Freely Available from IEEE
  • VTS 2013 Best Paper Award [includes 2 other awards]

    Publication Year: 2014, Page(s):1 - 3
    Request permission for commercial reuse | PDF file iconPDF (439 KB)
    Freely Available from IEEE
  • TTTC: Test technology technical council

    Publication Year: 2014, Page(s):1 - 3
    Request permission for commercial reuse | PDF file iconPDF (278 KB)
    Freely Available from IEEE
  • Fault simulation with test switching for static test compaction

    Publication Year: 2014, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    Static test compaction procedures reduce the number of tests in a given test set without reducing the fault coverage. Static test compaction procedures can use the set or the number of faults detected by each test as guidance. Fault simulation without or with limited fault dropping is needed for producing this information. However, it can be time consuming. To compute the information needed for gu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast evaluation of test vector sets using a simulation-based statistical metric

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB) | HTML iconHTML

    Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estim... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving CMOS open defect coverage using hazard activated tests

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Monte Carlo-based analog parametric fault modelling

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1464 KB) | HTML iconHTML

    The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to measure datasheet specifications. The lack of a comprehensive fault model that is computationally efficient makes the elimination of any tests or the use of lower-cost alternative tests too risky or too time-consuming. Monte Carlo simulations offer a general way to model parame... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A method for phase noise extraction from data communication

    Publication Year: 2014, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    Evaluating the phase noise of a data stream may be accomplished with the Fast Fourier Transform (FFT) of the signal, if the resolution is high enough, or captured using a mixer and local oscillator. To eliminate these requirements, we present a method for capturing phase noise amplitude from arbitrary bit stream data using a Time to Digital Converter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate and efficient method of jitter and noise separation and its application to ADC testing

    Publication Year: 2014, Page(s):1 - 5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Jitter is a crucial factor in high speed and high performance ADC testing. This paper proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics does not need to know before the processing. The alg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Innovative practices session 1C: Existing/emerging low power techniques

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (105 KB) | HTML iconHTML

    Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing methods for a write-assist disturbance-free dual-port SRAM

    Publication Year: 2014, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (489 KB) | HTML iconHTML

    In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodology consists of two test procedures. First, faulty cells suffering from wearout mechanisms in the SRAM system are isolated. Then, these faulty c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault modeling and test algorithm creation strategy for FinFET-based memories

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1065 KB) | HTML iconHTML

    FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New topic session 2B: Co-design and reliability of power electronic modules — Current status and future challenges

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB) | HTML iconHTML

    Power electronics covers various disciplines, especially semiconductor, circuit design, thermal design (heat transfer, fluid flow), electromagnetics (EMI, Inductors, transformers), digital electronics, control theory, and materials science in the context of packaging and reliability engineering. It also covers a wide range of power (mW to MW), temperature (−55C to 275C), frequencies (DC to ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Innovative practices session 2C: Advanced in yield learning

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB) | HTML iconHTML

    The onset of FinFET technology nodes brings with it additional challenges in ramping yields due to new defect behaviors and new hardships in the physical failure analysis process. This presentation highlights these challenges and makes the argument that improved scan based diagnosis capabilities that leverage a transistor level understanding of the cells will be necessary to combat these challenge... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (945 KB) | HTML iconHTML

    One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the indu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Alternative “safe” test of hysteretic power converters

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (849 KB) | HTML iconHTML

    This paper presents a novel alternative “safe” test method for line and load regulation specifications of hysteretic controlled switching power converters. These specifications have not been tested in production before because the conventional measurement techniques lead to huge voltage spikes during switching transients. Those voltage spikes are caused by energy accumulation from pa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accelerating capture of infrequent errors on ATE for silicon TV tuners

    Publication Year: 2014, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB) | HTML iconHTML

    Infrequent errors, such as unwanted glitches occurring once every a few seconds in silicon tuners, are very costly to capture in production due to long test time by the nature of the errors. The paper presents a novel scheme that reduces the test time from a few seconds to a few tens milliseconds. The scheme has been implemented to test millions of silicon TV tuners, and field defects caused by th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.