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Performance Analysis of Systems and Software, 2000. ISPASS. 2000 IEEE International Symposium on

Date 24-25 April 2000

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Displaying Results 1 - 25 of 31
  • 2000 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS (Cat. No.00EX422)

    Publication Year: 2000
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000 , Page(s): 207
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    Freely Available from IEEE
  • Do generational schemes improve the garbage collection efficiency?

    Publication Year: 2000 , Page(s): 58 - 63
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (276 KB)  

    Recently, most research efforts on garbage collection have concentrated on reducing pause times. However, very little effort has been spent on the study of garbage collection efficiency, especially generational garbage collection which was introduced as a way to reduce garbage collection pause times. In this paper a detailed study of garbage collection efficiency in generational schemes is present... View full abstract»

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  • CommBench-a telecommunications benchmark for network processors

    Publication Year: 2000 , Page(s): 154 - 162
    Cited by:  Papers (62)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (440 KB)  

    The paper presents a benchmark, CommBench, for use in evaluating and designing telecommunications network processors. The benchmark applications focus on small, computationally intense program kernels typical of the network processor environment. The benchmark is composed of eight programs, four of them oriented towards packet header processing and four oriented towards data stream processing. The... View full abstract»

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  • Simplified workload characterization using unified prediction

    Publication Year: 2000 , Page(s): 163 - 171
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (352 KB)  

    Quantitative workload characterization is essential to high performance computer architecture design. Unfortunately, quantitative results are typically hard to interpret, reproduce and compare, due to the staggering amount of detail inherent in modern architecture. Source language, compiler technology target ISA, and micro-architecture, intertwined with system aspects such as memory hierarchy and ... View full abstract»

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  • A new approach in the analysis and modeling of disk access patterns

    Publication Year: 2000 , Page(s): 172 - 177
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    While in previous work we have demonstrated that disk arrival patterns are consistent with self-similarity and have provided a physical explanation for the self-similar phenomenon in disk arrival patterns, the authors now deal with the analysis and modeling of disk access patterns. We provide visual and mathematical evidence showing that the same bursty behavior observed in the time series can als... View full abstract»

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  • Accurate simulation and evaluation of code reordering

    Publication Year: 2000 , Page(s): 13 - 20
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (364 KB)  

    The need for bridging the ever growing gap between memory and processor performance has motivated research for exploiting the memory hierarchy effectively. An important software solution called code reordering produces a new program layout to better utilize the available memory hierarchy. Many algorithms have been proposed. They differ based on: 1) the code granularity assumed by the reordering al... View full abstract»

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  • Performance evaluation of middleware bridging technologies

    Publication Year: 2000 , Page(s): 34 - 39
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (264 KB)  

    This paper provides a state-of-the-art study of bridging between different middleware technologies. Two DCOM-CORBA bridges, IONA OrbixCOMet and Visual Edge ObjectBridge, as well as a DCE-CORBA bridge by Inprise are tested and evaluated. Several configurations, depending on the number of machines and location of the bridge, are employed and two languages (C++ and Java) are used. The results show th... View full abstract»

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  • Issues in the design of store buffers in dynamically scheduled processors

    Publication Year: 2000 , Page(s): 76 - 87
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (512 KB)  

    Processor performance can be sensitive to load-store ordering, memory bandwidth, and memory access latency. A store buffer is a mechanism that exists in many current processors to accomplish one or more of the following: store access ordering, latency hiding, and data forwarding. Different policies that govern store buffer behavior can affect overall processor performance. However, the performance... View full abstract»

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  • A server performance model for static Web workloads

    Publication Year: 2000 , Page(s): 201 - 206
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    The paper describes a queuing network model for a multiprocessor system running a static Web workload such as SPECweb96. The model includes architectural details of the Web server in terms of multilevel cache hierarchy, processor bus, memory pipeline, PCI bus based I/O subsystem, and bypass I/O-memory path for DMA transfers. The model is based on detailed measurements from a baseline system and a ... View full abstract»

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  • Performance scalability in multiprocessor systems with resource contention

    Publication Year: 2000 , Page(s): 129 - 138
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (464 KB)  

    Multiple processes may contend for shared resources such as variables stored in the shared memory of a multiprocessor system. Mechanisms required to preserve data consistency on such systems often lead do a decrease in system performance. This research focuses on controlling shared resource contention for achieving high capacity and scalability in multiprocessor based applications that include tel... View full abstract»

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  • Invocation profile characterization of Java applications

    Publication Year: 2000 , Page(s): 116 - 122
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    Low performance of Java code execution (J. Gosling et al., 1996) has risen in the computer science community the awareness of the need for reengineering. This is mainly due to the software layer called Java Virtual Machine (T. Lindholm and F. Yellin, 1997), which allows Java applications to be multiplatform, but also to object oriented languages features, that impose a higher performance cost than... View full abstract»

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  • A practitioner report on the evaluation of the performance of the C, C++ and Java compilers on the OS/390 platform

    Publication Year: 2000 , Page(s): 40 - 45
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (240 KB)  

    The performance of C, C++ and JavaTM applications on the OS/390(R) platform is becoming an increasingly important issue as customers consolidate their server applications written in these languages on an OS/390 POSIX compliant system. With applications that run on multiple platforms such as the Lotus(R) DominoTM Server and SAP R/3 AppServer, customers have the ability to comp... View full abstract»

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  • Methodology to optimize the cost/performance of disk subsystems

    Publication Year: 2000 , Page(s): 109 - 115
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (280 KB)  

    The storage hierarchy plays a major role in the price and performance of high-end enterprise servers. In fact, the total price of a high-end server's hardware is dominated by its memory and disk configuration. Similarly, the performance is significantly influenced by the design and configuration of the server's memory and disk subsystems. Given these realities, the design and development of future... View full abstract»

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  • Checking order-insensitivity using ternary simulation in synchronous programs

    Publication Year: 2000 , Page(s): 52 - 57
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    In synchronous systems, new asynchronous distribution schemes are introduced. Properties can be established in order to distribute a program with weak synchronization. This paper deals with automatic verification of the order-insensitive property. Order-insensitivity is an important property introduced in synchronous systems by analogy with delay-insensitivity in asynchronous hardware. An algorith... View full abstract»

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  • Mobile functionality in a pervasive world

    Publication Year: 2000 , Page(s): 178 - 183
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (244 KB)  

    K. Eustice et al. (1999) presented the concept of a universal information appliance (UIA), a device capable of dynamically hosting tailored interfaces to the pervasive computing environment. The paper extends this concept by allowing the user to change, modify or improve the tailored interfaces available. This will enable an individual to dynamically create a user interface on the fly and to use i... View full abstract»

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  • Extracting fine-grain profiles of in-order executions of instruction level parallel programs

    Publication Year: 2000 , Page(s): 7 - 12
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (292 KB)  

    Optimizing compilers targeted to instruction level parallel (ILP) architectures schedule program instructions in such a way so as to minimize the number of execution stalls, called bubbles, that occur during program execution because of hazards. These bubbles are estimated by compilers on the basis of the target processor functional model. Unfortunately, these functional models are often inaccurat... View full abstract»

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  • A quantitative simulator for dynamic memory managers

    Publication Year: 2000 , Page(s): 64 - 69
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (284 KB)  

    In the last thirty years, several dynamic memory management schemes have been proposed. Such schemes include first fit, best fit, segregated fit, and buddy systems. Because the performance (speed and memory utilization) of each scheme differs, software engineers often face difficult choices in selecting the most suitable approach for their applications. In this paper, a quantitative simulator for ... View full abstract»

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  • Performance evaluation of real-time scheduling on a multicomputer architecture

    Publication Year: 2000 , Page(s): 28 - 33
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (256 KB)  

    The complexity of some real-time applications demands high performance computer architectures. Multicomputer architectures have a potential for high performance and reliability because of their expressive number of processors and communication channels. Therefore, they are natural candidates for supporting complex real-time computing. This paper presents a performance evaluation of real-time sched... View full abstract»

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  • Instruction overhead and data locality effects in superscalar processors

    Publication Year: 2000 , Page(s): 95 - 100
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (312 KB)  

    To reduce software development and maintenance costs, programmers are increasingly using object oriented programming languages, such as C++, and relying on highly flexible data structures, such as linked lists. Object oriented programming languages provide features that help manage complex software systems, but object oriented programs tend to suffer increased instruction counts, e.g. due to gener... View full abstract»

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  • An analytical model for loop tiling and its solution

    Publication Year: 2000 , Page(s): 146 - 153
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (300 KB)  

    The authors address the problem of estimating the performance of loop tiling, an important program transformation for improved memory hierarchy utilization. We introduce an analytical model for estimating the memory cost of a loop nest as a rational polynomial in tile size variables. We also present a constant-time algorithm for finding an optimal solution to the model (i.e., for selecting optimal... View full abstract»

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  • Some observations based on simple models of MP scaling

    Publication Year: 2000 , Page(s): 123 - 128
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (268 KB)  

    The emergence of large shared memory multiprocessor systems offer the potential of accelerating the pace of ever increasing system performance. On the one hand, it seems simple: add more processors, get more performance. On the other hand, it is quite difficult, as efficient scaling of workloads to large numbers of processors is a nontrivial challenge. Nevertheless, the way we use these very large... View full abstract»

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  • DB2 for OS/390 V5 vs. V6 outer join performance

    Publication Year: 2000 , Page(s): 46 - 51
    Cited by:  Papers (9)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (220 KB)  

    The outer join operation is one of the most frequently used operations in a relational database management system. It becomes even more important in data warehouse and business intelligence applications. The processing of outer join of very large relations is a very costly operation. Therefore, a lot of effort has been expended in the development and implementation of optimization techniques to im... View full abstract»

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  • Design alternatives for scalable Web server accelerators

    Publication Year: 2000 , Page(s): 184 - 192
    Cited by:  Papers (3)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (532 KB)  

    We study design alternatives for, and describe implementations and performance of, a scalable and highly available Web server accelerator. The accelerator runs under an embedded operating system and improves Web server performance by caching data. The basic design alternatives include a content router or a TCP router (without content routing) in front of a set of Web cache accelerator nodes, with ... View full abstract»

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  • Performance tradeoffs in sequencer design on a new G4 PowerPCTM microprocessor

    Publication Year: 2000 , Page(s): 88 - 94
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (236 KB)  

    The microprocessor discussed in this paper is a new member of the G4 family of PowerPC microprocessors with AltiVecTM enhanced technology, intended for high performance desktop systems. This four-way superscalar design is more deeply pipelined than previous designs in order to achieve greater frequency. The challenge in increasing frequency is to translate most or all of that increase i... View full abstract»

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