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Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

Date 27-30 March 2000

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  • Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)

    Publication Year: 2000
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  • A Design Automation Roadmap for EUROPE

    Publication Year: 2000 , Page(s): 510
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  • The future of flexible HW platform architectures

    Publication Year: 2000 , Page(s): 634
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  • Index of authors

    Publication Year: 2000 , Page(s): 767 - 770
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  • A BDD-based satisfiability infrastructure using the unate recursive paradigm

    Publication Year: 2000 , Page(s): 232 - 236
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB)  

    Binary Decision Diagrams have been widely used to solve the Boolean satisfiability (SAT) problem. The individual constraints can be represented using BDDs and the conjunction of all constraints provides all satisfying solutions. However, BDD-related SAT techniques suffer from size explosion problems. This paper presents two BDD-based algorithms to solve the SAT problem that attempt to contain the growth of BDD-size while identifying solutions quickly. The first algorithm, called BSAT, is a recursive, backtracking algorithm that uses an exhaustive search to find a SAT solution. The well known unate recursive paradigm is exploited to solve the SAT problem. The second algorithm is exploited to solve the SAT problem. The second algorithm, called INCOMPLETE-SEARCH-USAT (abbreviated IS-USAT), incorporates an incomplete search to find a solution. The search is incomplete inasmuch as it is restricted to only those regions that have a high likelihood of containing the solution, discarding the rest. Using our techniques we were able to find SAT solutions not only for all MCNC&ISCAS benchmarks, but also for a variety of industry standard designs View full abstract»

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  • Power and delay reduction via simultaneous logic and placement optimization in FPGAs

    Publication Year: 2000 , Page(s): 202 - 207
    Cited by:  Papers (2)  |  Patents (3)
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    Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology the lack of information on the physical implementation during logic synthesis has caused mismatches between the final circuit characteristics (delay, power and area) and those predicted by logic synthesis. In this paper, we present a technique that tightly links the logic and physical domains-we combine logic and placement optimization in a single step. The combined algorithm is based on simulation annealing and hence, very amenable to new optimization goals or constraints. Two types of moves, directed towards global reduction in the cost function (linear congestion), are accepted by the simulated annealing algorithm: (1) logic optimization steps consisting of removing or replacing redundant wires in a circuit using functional flexibilities derived from SPFDs and (2) the placement optimization steps consisting of swapping a pair of blocks in the FPGA. Feedback from placement is very valuable in making an informed choice of a target wire during logic optimization moves. Experimental results demonstrate the efficacy of our approach over the placement independent approach View full abstract»

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  • Automatic lighthouse generation for directed state space search

    Publication Year: 2000 , Page(s): 237 - 242
    Cited by:  Papers (3)  |  Patents (3)
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    Previous researchers have suggested the use of “lighthouses” to act as guides in directed state space search. The drawback of using lighthouses is that the user has to manually, derive them, through a potentially laborious examination of the design. Additionally specifying a large number of lighthouses results in wasted effort during the search. We present approaches to automatically generate high-quality lighthouses for hard-to-cover targets View full abstract»

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  • Analyzing real-time systems

    Publication Year: 2000 , Page(s): 243 - 248
    Cited by:  Papers (1)
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    Temporal logic model checking is a technique for the automatic verification of systems against specifications. Besides the correctness of safety and liveness properties it is often important to determine critical answer and delay times of systems, especially if they are embedded in a real-time environment. In this paper we present an approach which allows the verification as well as the timing analysis of real-time systems. The systems are described as networks of communicating time-extended finite state machines (I/O-interval structures). We use a compact symbolic representation to obtain efficient analysis algorithms View full abstract»

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  • Assessing the cost effectiveness of integrated passives

    Publication Year: 2000 , Page(s): 539 - 543
    Cited by:  Papers (1)
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    Passive components integrated into a high-density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted onto the system board. Still, this technology is perceived as being “too risky” and not cost effective. In this paper we propose a “passives optimized” solution combining the advantages from both SMD and integrated technology and avoiding the respective drawbacks. Exemplified by a GPS receiver front end, we present a methodology to assess the possible benefits when using the mixed technology View full abstract»

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  • Designing closer to the edge [deep submicron processes]

    Publication Year: 2000 , Page(s): 636 - 637
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    Summary form only given. Modern deep submicron CMOS processes cost Θ or more to develop, qualify and deploy. Yet the incremental impact of each technology generation has been steadily decreasing due to a variety of phenomena such as increasing wire delay, power dissipation and reliability limits, and increasing process tolerances. We need to make better use of existing and future manufacturing processes in order to recoup our investment. It is often possible to obtain more performance out of an existing technology by better understanding of the process tolerances and trading off functional yield vs. performance. Given the above, it is clear that we need to understand and model design tolerances arising from processing variations. Until recently, it was sufficient to model such process-induced variations as intra-die shifts in device performance. However, in the deep submicron regime, within-die wire and device variations are comparable to die-to-die variations. This results in the need for new characterization, modeling and analysis techniques to handle these variations. In this work we expand on the ideas above, review the important trends in design uncertainty which directly drives design tolerance and hence performance. We review a number of research and applied approaches to design for manufacturability. The need to track process tolerances as a technology matures is stressed. This tracking is important since it acts as an information conduit between design and fabrication groups and enables designers to adapt the design to lower tolerances where possible View full abstract»

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  • Architecture exploration of parameterizable EPIC SOC architectures

    Publication Year: 2000
    Cited by:  Patents (1)
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    Design Space Exploration (DSE) of programmable systems-on-chip (SOC) incorporating parameterizable processor cores is difficult due to the complex and intrinsically nonstructured interactions between different architectural features of the processor (such as wide parallelism, and deep pipelines), the compiler and the application. Changing different processor features implies generating detailed operation conflict information - represented as Reservation Tables (RTs). If done manually, it can be a very tedious and error prone task, especially for deep pipelines, with complex resource sharing and large nonstructured instruction sets. In this paper we use RTGEN, an approach for automatic generation of RTs, to drive rapid architectural exploration of a large number of designs. We present exploration experiments on a large set of VLIW-like EPIC architectures, for varying port sharing, number of functional units, multicycling units, and with varied latency configurations. Our experiments uncovered several non-intuitive architecture design points, giving the system-level designer further flexibility in exploration of programmable SOC architectures View full abstract»

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  • Formalized three-layer system-level reuse model and methodology for embedded data-dominated applications

    Publication Year: 2000 , Page(s): 92 - 98
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    In embedded data-dominated applications a global system-level data transfer and storage exploration phase is crucial in obtaining an efficient solution. We have developed a novel formalism to describe reusable blocks such that the essential part of the design exploration freedom is retained. This formalism is the basis for a system-level reuse methodology which allows to reuse large parts of the design as structural VHDL and describes the costly data access related constructs at higher levels in the code hierarchy. Compared to a reuse approach based on fixed blocks, considerable power and area savings can be obtained as demonstrated on real-life video and modem applications View full abstract»

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  • Stay away from minimum design-rule values [DFM in ultra-deep submicron processes]

    Publication Year: 2000 , Page(s): 71 - 72
    Cited by:  Papers (1)
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    The use of non-minimum design-rule values will be an important aspect of design for manufacturability in future ultra-deep submicron (UDSM) processes. EDA tools can and must assist in realizing appropriate design flows. Wire spreading and layout compaction tools are available today to implement preferred design-rule values on mask-layouts for enhanced manufacturability. The area of verification for manufacturability needs to be explored in the near future View full abstract»

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  • Detecting undetectable controller faults using power analysis

    Publication Year: 2000 , Page(s): 723 - 728
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    In systems consisting of interacting datapaths and controllers, the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This is not possible when the controller-datapath pair is an embedded system designed as a hard core. This work facilitates the testing of controller-datapath pairs in a truly integrated fashion. The key to the approach is a careful examination of the types of gate level stuck-at faults that can occur within the controller. A class of faults that are undetectable in an integrated test by traditional means is identified. These faults create faulty but functional circuits. The effect of these faults on power consumption is explored, and a method based on power analysis is given for detecting these faults. Analysis is given for three example systems View full abstract»

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  • A discrete-time battery model for high-level power estimation

    Publication Year: 2000 , Page(s): 35 - 39
    Cited by:  Papers (20)  |  Patents (6)
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    In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-time counterpart. The model is abstract and efficient enough to enable event-driven simulation of digital systems described at a very high level of abstraction and that include, among their components, also the power supply. Therefore, it can be successfully used for the purpose of battery life-time estimation during design optimization, as shown by the results we have collected on a meaningful case study. Experiments prove also that the accuracy of our model is very close to that provided by the corresponding Spice-level model View full abstract»

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  • Non-linear components for mixed circuits analog front-end

    Publication Year: 2000 , Page(s): 544 - 549
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    This paper presents the development of some front-end analog circuits for mixed signals systems. The paper proposes the use of externally linear internally nonlinear analog circuits. Using this approach, analog area is greatly reduced and circuits can be built on top of completely digital technologies. Experimental results in the analog and digital domain support the proposed approach to mixed circuits design View full abstract»

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  • Lower bounds on the power consumption in scheduled data flow graphs with resource constraints

    Publication Year: 2000
    Cited by:  Papers (1)
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    Summary form only given. The problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding is addressed. The estimated bound takes into account the effects of resource sharing. It is shown that by introducing Langrangian multipliers and relaxing the low power binding problem to the Assignment Problem, which can be solved in O(n 3), a tight and fast computable bound is achievable. Experimental results show the good quality of the bound. In most cases, deviations smaller than 5% from the optimal binding were observed. The proposed technique can for example be applied in branch and bound high-level synthesis algorithms for efficient pruning of the design space View full abstract»

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  • Reducing the complexity of defect level modeling using the clustering effect

    Publication Year: 2000 , Page(s): 640 - 644
    Cited by:  Papers (10)
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    Accounting for the clustering effect is fundamental to increasing the accuracy of defect level (DL) modeling. This result has long been known in yield modeling but, as far as known, only one DL model directly accounts for it. In this paper we improve this model, reducing its number of parameters from three to two by noticing that multiple faults caused by a single defect can also be modeled as additional clustering. Our result is supported by test data from a real production line View full abstract»

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  • Optimal hardware pattern generation for functional BIST

    Publication Year: 2000 , Page(s): 292 - 297
    Cited by:  Papers (6)  |  Patents (1)
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    Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as a hardware test pattern generator. Up to now, only linear feedback shift registers and accumulator based structures have been used for deterministic test pattern generation by reseeding. In this paper, a method is proposed which can be applied to general finite state machines. Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module. Experiments prove the effectiveness of the approach which outperforms previous results for accumulators, in terms of test size and test time, without sacrificing the fault detection capability View full abstract»

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  • Efficient resource arbitration in reconfigurable computing environments

    Publication Year: 2000 , Page(s): 560 - 566
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB)  

    In a multi-FPGA synthesis system, ideally the designer has only an abstract view of the board architecture. This abstract modeling of the underlying reconfigurable computer poses complex challenges to the synthesis and partitioning tools. Since the design specification is not constrained by the number of memory segments on the board or the number of pins between FPGAs, it is difficult for the CAD tools to transform the design into one that maps onto the multi-FPGA board. This paper describes an arbitration mechanism that bridges the abstraction between the implicit design and the reconfigurable architecture. Since this mechanism allows such architecture abstraction between the design and the board, it becomes easier to port a design from one target architecture to another. This arbitration mechanism introduces very little overhead in terms of area and delay. It has been used in data-dominated applications; in this paper fast Fourier transform (FFT) is shown as an illustrative example View full abstract»

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  • A generic architecture for on-chip packet-switched interconnections

    Publication Year: 2000 , Page(s): 250 - 256
    Cited by:  Papers (250)  |  Patents (37)
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    This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network View full abstract»

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  • Standards for system-level design: practical reality or solution in search of a question?

    Publication Year: 2000 , Page(s): 576 - 583
    Cited by:  Papers (15)
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    We address the issue of standards development for the system-level design space. System-level design IP re-use standards are key to the future of the VSIA. However, the concept of system-level standards has its share of sceptics: what role can standards play in this developing market segment? In response we present an overview of three standards in the system-level VC integration space, and describe two distinct industrial case studies to support their practicality View full abstract»

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  • A BIST scheme for on-chip ADC and DAC testing

    Publication Year: 2000 , Page(s): 216 - 220
    Cited by:  Papers (32)
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    In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection View full abstract»

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  • Automating RT-level operand isolation to minimize power consumption in datapaths

    Publication Year: 2000 , Page(s): 624 - 631
    Cited by:  Papers (10)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB)  

    Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation whose result is not used in the downstream circuit, power is being consumed for an otherwise redundant computation. Operand isolation is a technique to minimize the power overhead incurred by redundant operations by selectively blocking the propagation of switching activity through the circuit. This paper discusses how redundant operations can be identified concurrently to normal circuit operation, and presents a model to estimate the power savings that can be obtained by isolation of selected modules at the register-transfer (RT) level. Based on this model, an algorithm is presented to iteratively isolate modules, while minimizing the cost incurred by RTL operand isolation. Experimental results with power reductions of up to 30% demonstrate the effectiveness of the approach View full abstract»

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  • An object oriented design method for reconfigurable computing systems

    Publication Year: 2000 , Page(s): 692 - 696
    Cited by:  Papers (3)
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    We present a novel method for developing reconfigurable system targeted at embedded system applications. We show how an existing object oriented design method (MOOSE) has been adapted and enhanced to include reconfigurable hardware (FPGAs). Our work represents a significant advance over current embedded system design methods in that it integrates the use of reconfigurable hardware components with a systematic design method for complete systems. The objective is to produce an object oriented design methodology where system objects can be seamlessly implemented in either software or reconfigurable hardware View full abstract»

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