[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

21-25 Sept. 1992

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Displaying Results 1 - 25 of 123
  • A tutorial on GaAs vs silicon

    Publication Year: 1992, Page(s):281 - 287
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (487 KB)

    The physical properties of GaAs and silicon are described, and the advantages and disadvantages of GaAs over silicon in terms of physics are reported. The implications of physical properties and circuit techniques for computing and communication applications are addressed in terms of ASICs.<> View full abstract»

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  • Tutorial on design for testability

    Publication Year: 1992, Page(s):139 - 142
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (270 KB)

    Testability must be incorporated in all phases of an ASIC design, including wafer level, chip level, I/O level, and board/system level. Level-sensitive scan design (LSSD) is a design technique that uses latches and flip-flops that are level sensitive as opposed to edge triggered. The basic approach of LSSD is to make a sequential network appear like combinatorial logic during testing by logically ... View full abstract»

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  • Timing driven placement of pads and latches

    Publication Year: 1992, Page(s):30 - 33
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (446 KB)

    A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performanc... View full abstract»

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  • Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4)

    Publication Year: 1992
    Request permission for commercial reuse | |PDF file iconPDF (15 KB)
    Freely Available from IEEE
  • An analysis and design of an optimal programmable analog CMOS synapse

    Publication Year: 1992, Page(s):573 - 576
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (240 KB)

    Reports on a project to develop an optimally sized programmable analog CMOS synapse cell library which is readily available for the construction of a high-density VLSI neural network. A set of optimal design equations is derived from standard CMOS equations. The derivation of the design equations and the evaluation of the size (silicon area) and performance of the synapse cell are discussed View full abstract»

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  • Fast turn-around ASIC design environment with design assistant tools

    Publication Year: 1992, Page(s):267 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (272 KB)

    A fast turn-around design environment is described. A set of design assistant tools is implemented and integrated in the system. These programs help designers to verify circuit function across different design levels, locate the over-loaded drivers, calculate power dissipation, and summarize detail data of the design. The functions of these tools are described. An example is given View full abstract»

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  • Bus driver IC for use in vehicle multiplexing communications

    Publication Year: 1992, Page(s):79 - 82
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (328 KB)

    A prototype of a bus driver IC for use in communications, and particularly suited in multiplexed bus operation in an automotive vehicle environment, has been developed. The bus driver consists of amplitude and time matched complementary current sources which minimize bus radio frequency radiation. Bus driving system analysis is presented, together with details of the bus driver IC design. The redu... View full abstract»

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  • A fuzzy neural network chip based on systolic array architecture

    Publication Year: 1992, Page(s):577 - 580
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware descrip... View full abstract»

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  • A standard cell set for delay insensitive VLSI design

    Publication Year: 1992, Page(s):123 - 126
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (300 KB)

    Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complex... View full abstract»

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  • Teaching ASIC design with FPGAs

    Publication Year: 1992, Page(s):271 - 274
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (236 KB)

    The University of Southern Colorado has developed a VLSI design program that has been used in several courses and design projects. ASICs employing field programmable gate array (FPGA) technologies are used for implementation of the resulting designs. Designs of a 4-b computer, a microcode CPU, and a floating point coprocessor are discussed. FPGA reprogrammability and fast turn-around times have pr... View full abstract»

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  • 4B5B decoder for FDDI

    Publication Year: 1992, Page(s):83 - 86
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    A 2-μm CMOS FDDI (fiber distributed data interface) 4B5B decoder with an elastic self-timed buffer is presented. The design operates at 125 MHz and meets the requirements specified by the ANSI X3.139-1987 standard. The characteristic features of this design are logical simplicity, compact silicon area, operational speed well above that specified for FDDI, and metastable operation resistivity. T... View full abstract»

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  • Micro data flow

    Publication Year: 1992, Page(s):301 - 304
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    Digital computation systems based on transition signal framework have many advantages. The synthesis of a self-timed physical design from a high-level dataflow specification is examined. The approach maps tokens that travel on data and control arcs of a dataflow graph into transitions of the event signals. The two-phase event signal transition style is employed, where both the rising edge and the ... View full abstract»

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  • Testability measure and analysis

    Publication Year: 1992, Page(s):129 - 138
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (684 KB)

    Testability is a major concern in the design of VLSICs and ASICs. Testing can be simplified and made more effective if design for testability (DFT) techniques are incorporated into the design. There are many methods to analyze, measure, and evaluate the effectiveness of a DFT technique. A review of some of the widely used methods for measuring testability is presented View full abstract»

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  • The design approach to ASICs in education

    Publication Year: 1992, Page(s):275 - 278
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    The approach used at Nottingham Polytechnic to develop the expertise of ASIC designers at the undergraduate level is described. It is argued that an integrated approach to computer aided engineering (CAE) is important, that the interface between the ASIC and other components is necessary, and that board-level simulation is an essential element in the process. One of the design studies is described View full abstract»

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  • VLSI CMOS implementation of the shuffleout ATM switch interconnection matrix

    Publication Year: 1992, Page(s):87 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (432 KB)

    The VLSI design and implementation of the shuffleout broadband switch interconnection matrix are described in order to show its feasibility with current CMOS technology. It satisfies simultaneously the requirements for ATM switching and for ASIC industrial manufacturing. The shuffleout routing principles are briefly summarized and the design approach is discussed. The switching element major block... View full abstract»

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  • Design of a 50 MFIPS fuzzy controller ASIC

    Publication Year: 1992, Page(s):305 - 308
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (268 KB)

    The design of a 50×106 fuzzy inferences per second (FIPS) controller is presented. Based on a 1.2-μm CMOS technology, the controller supports 64 rules, four inputs, and two outputs. An appropriate number of copies can be cascaded for extensions beyond these specifications. The design uses no custom-designed blocks. Performance is obtained through a streamlined architecture, par... View full abstract»

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  • Integrating a full custom microprocessor in a user defined ASIC array as a fully diffused core

    Publication Year: 1992, Page(s):451 - 454
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    A MC68000 microprocessor has been embedded in a gate array device as a fully diffused core, allowing ASIC designers to combine up to 60 K gates of user-defined logic, verified within the Verilog simulation environment. The MC68000 can be implemented on other array sizes utilizing the same flow. For each new array the layout flow is repeated to generate a new base wafer that includes the MC68000. T... View full abstract»

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  • A VLSI-chip for a hardware-accelerator for the simplex-method

    Publication Year: 1992, Page(s):553 - 556
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (252 KB)

    A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employing standard floating point units (FPUs), RAMs, and custom VLSI chips. It has been designed for use in... View full abstract»

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  • Image processing ASIC for real-time contrast enhancement

    Publication Year: 1992, Page(s):197 - 200
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    An ASIC chip set that implements adaptive local contrast enhancement for real-time image processing is presented. The contrast enhancement is based on a nonlinear mapping M(A,σ,P), where A is an average, σ is a standard deviation, and P is a center pixel over a 9×9 window. The throughput rate is 100 ns per pixel. A dynamic programming ... View full abstract»

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  • Pre-design consideration and evaluation for ASICs

    Publication Year: 1992, Page(s):249 - 252
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    A new design methodology is used to evaluate the difference in performance when implementing the same design using two different ASIC libraries. Multiple dimensions of the design space are considered yielding a better evaluation of the design in hand. An arithmetic logic unit (ALU) is designed using both a standard cell library and a data path library. A cost function is evaluated for both cases a... View full abstract»

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  • A serial/parallel color matrix, 2D convolution and 9-Tap filter ASIC with a systems perspective

    Publication Year: 1992, Page(s):181 - 184
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (240 KB)

    A single chip that can perform three-channel 1×4 serial color matrixing, 3×4 color matrixing, 3×3 (2-D) convolution, and a nine-TAP FIR filter has been designed in a 1-μm gate array. The chip operates at 25 MHz and is useful for color optimization in scanning applications using linear CCD sensors, in electronic imaging applications using area sensors, and in a variety of image... View full abstract»

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  • An ETL gate array implementation of a 2.5 Gb/s, 48-bit wide, channel programmable demultiplexer for fiber optic data transmission

    Publication Year: 1992, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    Describes unique circuit and logic design techniques in the implementation of a 48-channel programmable demultiplexer using a mature, high-yielding, bipolar ECL gate array for data transmission at 2.5 Gb/s. The new high-frequency macros and the unique design of the timing control circuitry enable a mature process technology to be used to more than double the operating rate of the technology compar... View full abstract»

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  • A fully integrated characterization and management system for ASIC libraries

    Publication Year: 1992, Page(s):245 - 248
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (268 KB)

    A system is presented that supplies ASIC libraries for multiple CAD systems. Characterizations of macro cells and library translators into ASIC design systems such as logic delay simulators, wire delay calculators, design rule checkers, and logic syntheses are fully integrated with a central object oriented database. This data management system (DMS) automatically appends revisions, maintains data... View full abstract»

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  • An implementation of a clock-tree distribution scheme for high-performance ASICs

    Publication Year: 1992, Page(s):26 - 29
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (252 KB)

    An implementation of a multilevel balanced clock-tree distribution scheme that improves the performance of ASICs considerably is described. Layout process and the CAD tools are briefly described, and the results are tabulated for differing complexities of real customer designs. The focus of this clock-tree distribution scheme is on minimizing the clock skew, on reducing the total clock delay from ... View full abstract»

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  • A minimal hardware overhead BIST data compaction scheme

    Publication Year: 1992, Page(s):368 - 371
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    Existing data compaction schemes for built-in self-test (BIST) usually impose substantial hardware overhead. A minimal hardware overhead data compaction scheme is proposed that can achieve reasonably small aliasing with a hardware requirement as low as a one-stage linear feedback shift register (LFSR). Multiple signatures are checked, and all reference-signatures are made identical resulting in si... View full abstract»

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