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[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

21-25 Sept. 1992

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Displaying Results 1 - 25 of 123
  • Timing driven placement of pads and latches

    Publication Year: 1992, Page(s):30 - 33
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performanc... View full abstract»

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  • Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (15 KB)
    Freely Available from IEEE
  • An ASIC architecture for implementing low-level communication circuits

    Publication Year: 1992, Page(s):537 - 541
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A flexible architecture model is presented to implement low-layer protocols into silicon. This model is especially well adapted to real-time features (as in industrial and control-command LANs) and provides a significant increase in the message processing speed. The goal is to propose a systematic approach to the problem of communication protocol implementation in hardware: the design methodology ... View full abstract»

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  • Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

    Publication Year: 1992, Page(s):545 - 548
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughp... View full abstract»

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  • Embedded 6 bit flash converter design for digital stereo sound decoder

    Publication Year: 1992, Page(s):391 - 395
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    The design of a 25-MHz, 6-b flash converter embedded in a customized digital signal processor for decoding of digital stereo sound broadcast on terrestrial TV channels is described. The design is based upon an offset cancellation comparator which obviates the need for large storage capacitors traditionally used for input offset reduction, and makes the design easier to fabricate in standard CMOS t... View full abstract»

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  • The COREWARE methodology: building a 200 MFLOP processor in 9 man months

    Publication Year: 1992, Page(s):549 - 552
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    Utilizing the COREWARE methodology, a 163-MFLOP graphics transformation processor is realized in a 0.7-μm two-layer metal CMOS process operating at 40 MHz. The COREWARE methodology allows the processor to be specified, designed, and implemented in nine man months. The graphics processor provides 3.3 million transformed, perspective divided, clip tested 3D vertices per second. The matrix multipl... View full abstract»

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  • Pre-design consideration and evaluation for ASICs

    Publication Year: 1992, Page(s):249 - 252
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A new design methodology is used to evaluate the difference in performance when implementing the same design using two different ASIC libraries. Multiple dimensions of the design space are considered yielding a better evaluation of the design in hand. An arithmetic logic unit (ALU) is designed using both a standard cell library and a data path library. A cost function is evaluated for both cases a... View full abstract»

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  • A high speed metal programmable static RAM compiler for 0.7 μm CMOS gate array

    Publication Year: 1992, Page(s):505 - 508
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A static RAM compiler has been developed for a new 0.7 micron Leff CMOS gate array. The compiler is fully metal programmable and can compile RAMs from 8 bits to 64 K bits with typical access times of 4 ns to 10 ns, respectively. It supports partially decoded RAMs and variable aspect ratios. The compiler is well integrated into CAD tools View full abstract»

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  • Using VHDL for modeling and design of processing units

    Publication Year: 1992, Page(s):315 - 326
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    The use of VHSIC hardware description language (VHDL) for the design and implementation of a CPU structure is presented. The CPU is described at the behavioral level. This design phase is followed by the actual design of the CPU. For this purpose, a more detailed description of hardware is developed at the dataflow level, and includes register and bus structure details of the hardware. Simulation ... View full abstract»

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  • An 8-10-bit, 1-40 MHz analog signal processor with configurable performance for electronic imaging applications

    Publication Year: 1992, Page(s):396 - 400
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    An 8-10-b, 1-40-MHz analog signal processing ASIC that performs correlated double sampling (CDS), variable gain adjustment, periodic DC restoration, analog inversion, and analog multiplexing for black level insertion or synchronization is described. The ASIC has been developed in a configurable bipolar analog array for electronic imaging applications and is optimized for image sensor output rates ... View full abstract»

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  • A VLSI-chip for a hardware-accelerator for the simplex-method

    Publication Year: 1992, Page(s):553 - 556
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employing standard floating point units (FPUs), RAMs, and custom VLSI chips. It has been designed for use in... View full abstract»

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  • A circuit component placer for optimizing layout with arbitrarily shaped rectilinear and soft blocks

    Publication Year: 1992, Page(s):46 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A novel circuit component placement algorithm to place arbitrarily shaped rectilinear and soft blocks is proposed. Experimental results on randomly generated cases and industrial examples demonstrate that the algorithm can both find a very compact placement and minimize the wire length View full abstract»

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  • Grouping variables into multiport memories for ASIC data path synthesis

    Publication Year: 1992, Page(s):162 - 165
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Grouping variables into multiport memories is an essential step for multiport memory based data path synthesis. The proposed system, GMD, not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem is formulated as a 0-1 integer linear programming (ILP) problem. Experiments on... View full abstract»

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  • Comprehensive structural testing of ASIC macrocells, a comparative analysis

    Publication Year: 1992, Page(s):143 - 148
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A comparative analysis of three test generation methods for designs based on CMOS ASIC macrocells is presented. These methods are (1) stuck-at tests, (2) IDDQ tests; and (3) crosscheck tests. The fault modeling technique for each method is described. The test generated by using the fault model of each method is used to compare the completeness of the methods in terms of actual defect coverage. Con... View full abstract»

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  • ASIC implementation of a 16-kbps waveform coder using adaptive vector quantization

    Publication Year: 1992, Page(s):72 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The development of an adaptive vector quantizer (AVQ) codec chip using Open Architecture Silicon Implementation System (OASIS) tools is described. The goal is development of a 16-kb/s AVQ coder prototype system which can be used as an alternative to the currently used 32-kb/s adaptive delta pulse code modulation (ADPCM). The AVQ semicustom chip layout uses 1.2-μm CMOS technology, and consists o... View full abstract»

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  • A fully integrated characterization and management system for ASIC libraries

    Publication Year: 1992, Page(s):245 - 248
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A system is presented that supplies ASIC libraries for multiple CAD systems. Characterizations of macro cells and library translators into ASIC design systems such as logic delay simulators, wire delay calculators, design rule checkers, and logic syntheses are fully integrated with a central object oriented database. This data management system (DMS) automatically appends revisions, maintains data... View full abstract»

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  • Evaluating VHDL-based ASIC synthesis tools

    Publication Year: 1992, Page(s):253 - 256
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    An evaluation of VHSIC hardware description language (VHDL) based design tools using synthesis vs. schematic capture-macrocell approach to field programmable gate array (FPGA) design is described. The risk of committing to an ASIC technology for a project that may or may not go into production can be mitigated by using FPGAs. Designing with VHDL allows flexibility if the decision is made to migrat... View full abstract»

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  • Development and simulation of a 4080-point Winograd fast Fourier transform processor

    Publication Year: 1992, Page(s):205 - 208
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    By using the Good-Thomas prime factor algorithm, 15-, 16-, and 17-point Winograd algorithm fast Fourier transform (FFT) processors are combined to perform 4080-point FFTs. The circuits are analyzed in VHSIC hardware description language (VHDL), simulated, and laid out in MAGIC for fabrication through MOSIS. The VHDL simulation includes behavioral modeling and the simulation of 15-, 16-, 17-, and 4... View full abstract»

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  • The design approach to ASICs in education

    Publication Year: 1992, Page(s):275 - 278
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The approach used at Nottingham Polytechnic to develop the expertise of ASIC designers at the undergraduate level is described. It is argued that an integrated approach to computer aided engineering (CAE) is important, that the interface between the ASIC and other components is necessary, and that board-level simulation is an essential element in the process. One of the design studies is described View full abstract»

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  • Designing programmable hearing aids using BiCMOS

    Publication Year: 1992, Page(s):411 - 414
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    BiCMOS is used for digitally programmable hearing aids. The analog signal processing function is implemented with bipolar circuits to provide amplification, automatic gain control (AGC), and filtering in the time-continuous domain, while digital logic and memory are implemented using standard cell CMOS. With on-chip chrome-silicon resistors and poly-to-p+ capacitors, a 17.8-mm... View full abstract»

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  • VLSI CMOS implementation of the shuffleout ATM switch interconnection matrix

    Publication Year: 1992, Page(s):87 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The VLSI design and implementation of the shuffleout broadband switch interconnection matrix are described in order to show its feasibility with current CMOS technology. It satisfies simultaneously the requirements for ATM switching and for ASIC industrial manufacturing. The shuffleout routing principles are briefly summarized and the design approach is discussed. The switching element major block... View full abstract»

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  • Ramgen: a dual port static RAM generator

    Publication Year: 1992, Page(s):509 - 512
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    An automatic dual port static RAM (DPSRAM) generator based on a process-independent design methodology for double metal CMOS technology is described. An innovative architecture, using modular structures and cutoff transistors, has been designed to maintain the same performance independent of the array size, and to minimize the basic cell area. The use of the process-independent approach allows for... View full abstract»

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  • Integrating a full custom microprocessor in a user defined ASIC array as a fully diffused core

    Publication Year: 1992, Page(s):451 - 454
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A MC68000 microprocessor has been embedded in a gate array device as a fully diffused core, allowing ASIC designers to combine up to 60 K gates of user-defined logic, verified within the Verilog simulation environment. The MC68000 can be implemented on other array sizes utilizing the same flow. For each new array the layout flow is repeated to generate a new base wafer that includes the MC68000. T... View full abstract»

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  • ASIC packaging directions

    Publication Year: 1992, Page(s):565 - 568
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Past and predicted future trends in ASIC packaging are examined. Specific issues addressed include ASIC packaging complexity; pin count; surface mount technology; pin grid arrays; quad flat packs; land grid arrays; tape automated bonding; and multichip modules View full abstract»

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  • Accurate VHDL libraries for ASIC design

    Publication Year: 1992, Page(s):327 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    The creation of a VHSIC hardware description language (VHDL) library with sign-off quality for a 0.8-μm CMOS ASIC technology is described. The methodology used, the problems encountered, and accuracy and performance are discussed View full abstract»

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