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2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)

27-29 Feb. 2000

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  • 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)

    Publication Year: 2000
    Request permission for commercial reuse | PDF file iconPDF (331 KB)
    Freely Available from IEEE
  • Discussions on the CORDIC processor using leading zeros detector

    Publication Year: 2000, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (169 KB)

    In this paper the application of CORDIC (COordinate Rotation DIgital Computer) processor using leading zeros detector (LZD) is discussed. In previous research, LZD was used in the normalization of the floating point number computation, also we find that it can be used in the CORDIC processor for reducing the number of iterations, deciding the sign of redundant number and speeding the computation o... View full abstract»

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  • Author index

    Publication Year: 2000, Page(s): 195
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    Freely Available from IEEE
  • An active substrate driver for mixed-voltage SOI systems on a chip

    Publication Year: 2000, Page(s):83 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    High-voltage transistors in SOI that coexist with traditional low-voltage transistors enable the development of mixed-voltage (high-voltage and low-voltage) systems-on-a-chip. The parasitic back-channel transistor, however, is a critical issue in these mixed-voltage single-chip systems. The presence of high-voltage can create a situation in which the parasitic back-channel device turns on and &ldq... View full abstract»

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  • Cycle-domain simulator for phase-locked loops

    Publication Year: 2000, Page(s):77 - 82
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools avail... View full abstract»

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  • Behavioral modeling of a SONET/SDH transceiver using HDLA

    Publication Year: 2000, Page(s):73 - 76
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    In order to reduce the number of design iteration for complex mixed signal telecommunication IC's, verification through full chip simulation is a must. The objective is to verify connectivity and functionality for the whole chip including the interface between analog and digital blocks. Efficient top level simulation required the use of a mixed mode (Analog and Digital) simulator. In addition, in ... View full abstract»

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  • Switching-induced substrate noise and mixed-signal receiver design

    Publication Year: 2000, Page(s):119 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    We use a stochastic model of the switching current to describe the power spectral density of current noise waveforms induced by digital switching events. We discuss common impedance paths, particularly arising from non-ideal properties of electronic packages, that couple this noise into the substrate of an integrated circuit. We derive estimates of the noise spectrum for modest digital power and t... View full abstract»

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  • Characteristics of linear-coded D/A converters

    Publication Year: 2000, Page(s):67 - 72
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    We evaluate the performance of flash D/A converters designed with a new approach based on linear coding of the weights. The evaluation is performed by estimating the relative performance of the new, linear-coded converter compared with thermometer coded, binary-scaled, and segmented converters. As a measure of performance we use glitch noise, which is of importance in high-speed D/A converter oper... View full abstract»

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  • A novel fully integrated fan controller for advanced computer systems

    Publication Year: 2000, Page(s):191 - 194
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and ... View full abstract»

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  • A current mode CMOS voltage reference

    Publication Year: 2000, Page(s):23 - 26
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    A current mode CMOS voltage reference uses a p-channel MOSFET threshold voltage extractor circuit to create a current that is inversely proportional to temperature. This current is summed with a current that is proportional to temperature into a resistor to create a voltage that is, to the first order, temperature independent. The output voltage is scalable by adjusting the size of the summing res... View full abstract»

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  • Use of switched buffers in very high-speed data converters

    Publication Year: 2000, Page(s):93 - 96
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    We present a new design approach for high resolution analog-to-digital converters operating at very high speeds. We show that using CMOS switches and the switched current technique are not convenient for advanced specifications. The switched buffer method proposed here offers new perspectives since it allows the designer to preserve accuracy even at high speeds of operation. The switched buffer co... View full abstract»

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  • Sensor plane processing for multiplex imaging

    Publication Year: 2000, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Digital imaging systems are fundamentally different from analog ones because they differentiate the measurement space and the reconstruction space. Multiplex systems use this separation to optimize source reconstruction. We consider the requirements imposed on sensor plane processors by multiplex imaging systems. We consider system flexibility, analog/digital split, A/D dynamic range, bandwidth, a... View full abstract»

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  • System design considerations of wideband multi-standard receiver for 3rd generation mobile system applications

    Publication Year: 2000, Page(s):103 - 108
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Mobile communications systems will evolve towards a third generation at the beginning of the new millenium. Third generation is built on the backward compatibility with the second generation networks. Thus wideband multi-standard receivers, which are able to operate according to multiple mobile communication standards, will be required by the third generation system users. This paper presents a nu... View full abstract»

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  • Body-driving as a low-voltage analog design technique for CMOS technology

    Publication Year: 2000, Page(s):113 - 118
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included View full abstract»

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  • RF CMOS mixer design and optimization for wideband CDMA application

    Publication Year: 2000, Page(s):45 - 50
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    This paper presents the design of a Gilbert downconversion mixer for wideband CDMA application. The mixer is designed using a 0.18 μm 1.5 V/3.3 V dual voltage digital CMOS technology. The design methodology is presented to achieve high linearity and low noise figure. A design flow is introduced targeting the automatic design and optimization for mixers View full abstract»

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  • Functional-based ATPG for path delay faults

    Publication Year: 2000, Page(s):159 - 164
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    A novel methodology for non-enumerative ATPG for path delay faults is presented. Tests are generated by manipulating, in a systematic yet simple way, sets of pairs of functions. Each pair of functions represents the constraints to be satisfied by the non-enumerative delay fault test for each time frame of a transition. A test that detects many faults is generated from each pair of functions. A cur... View full abstract»

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  • The design of 433 MHz class AB CMOS power amplifier

    Publication Year: 2000, Page(s):36 - 40
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper reports the design and simulation results of a 433 MHz Power Amplifier (PA) which is designed in a 0.5 μm CMOS technology and can provide variable gain modes. The PA consists of a driver and an output stage, and the gain is adjustable using digital codes. In this paper, 16.5 dB and 3.5 dB gain modes are chosen. This amplifier matches a 50 ohm load and provides 20 mW of output power a... View full abstract»

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  • D/A conversion with linear-coded weights

    Publication Year: 2000, Page(s):61 - 66
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion base... View full abstract»

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  • Substrate thermal model reduction for efficient transient electrothermal simulation

    Publication Year: 2000, Page(s):185 - 190
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A multiport RC network reduction technique based on congruence transformation was developed specifically for improving the efficiency of temperature calculation in electrothermal simulations. This technique helps reduce the size of the three-dimensional lumped RC network, which is commonly used to model substrate heat conduction, while still preserving the input/output characteristics at the port ... View full abstract»

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  • A delta-sigma modulation based BIST scheme for mixed-signal systems

    Publication Year: 2000, Page(s):147 - 152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    We present the architecture and analysis of a built-in self-test (BIST) scheme that targets mixed-signal system-on-chip (SOC) designs. The basic idea is to employ simple yet high-tolerant digital-to-analog (DA) and analog-to-digital (AD) conversion techniques for on-chip stimulus generation and response acquisition, and to utilize on-chip programmable cores for digital signal processing required f... View full abstract»

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  • Optically reconfigurable processors

    Publication Year: 2000
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    Reconfigurable processors, like the field programmable gate arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its internal ... View full abstract»

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  • Preliminary circuits for Smart Dust

    Publication Year: 2000, Page(s):87 - 92
    Cited by:  Papers (21)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper we present a miniature system that is being designed for the Smart Dust project to test the communication link and simulate basic functionality. The system includes an optical receiver to process the incoming laser signal, digital circuits to generate a pseudorandom number sequence, a corner cube reflector (CCR) to passively transmit data to the base station, and a charge pump to gen... View full abstract»

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  • Modeling and analysis of substrate coupled noise in pipelined data converters

    Publication Year: 2000, Page(s):125 - 130
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are inv... View full abstract»

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  • Biasing analog circuits using the nullor concept

    Publication Year: 2000, Page(s):27 - 30
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    In an attempt to provide an efficient biasing scheme for analog circuits, this paper addresses the problem of designing the correct bias-circuitry using the nullor concept. First, the rules for biasing nullators and norators are introduced. Second, a technique for efficiently biasing analog circuits is proposed. Finally, the proposed biasing technique is demonstrated by implementing it in practica... View full abstract»

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  • Design guidelines for optimized nested Miller compensation

    Publication Year: 2000, Page(s):97 - 102
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    The nested Miller compensation of three-stage amplifiers is reviewed by using a novel and simple design-oriented approach allowing the control of the overall phase margin as well as that of each internal loop. Furthermore, a novel technique using nulling resistors to remove the RHP zeroes is discussed which greatly improves frequency and slew-rate performance, without increasing the power consumpt... View full abstract»

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