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Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on

Date 27-29 Feb. 2000

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Displaying Results 1 - 25 of 42
  • 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)

    Publication Year: 2000
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    Freely Available from IEEE
  • Discussions on the CORDIC processor using leading zeros detector

    Publication Year: 2000, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (169 KB)

    In this paper the application of CORDIC (COordinate Rotation DIgital Computer) processor using leading zeros detector (LZD) is discussed. In previous research, LZD was used in the normalization of the floating point number computation, also we find that it can be used in the CORDIC processor for reducing the number of iterations, deciding the sign of redundant number and speeding the computation o... View full abstract»

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  • Author index

    Publication Year: 2000, Page(s): 195
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    Freely Available from IEEE
  • System design considerations of wideband multi-standard receiver for 3rd generation mobile system applications

    Publication Year: 2000, Page(s):103 - 108
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Mobile communications systems will evolve towards a third generation at the beginning of the new millenium. Third generation is built on the backward compatibility with the second generation networks. Thus wideband multi-standard receivers, which are able to operate according to multiple mobile communication standards, will be required by the third generation system users. This paper presents a nu... View full abstract»

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  • An active substrate driver for mixed-voltage SOI systems on a chip

    Publication Year: 2000, Page(s):83 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    High-voltage transistors in SOI that coexist with traditional low-voltage transistors enable the development of mixed-voltage (high-voltage and low-voltage) systems-on-a-chip. The parasitic back-channel transistor, however, is a critical issue in these mixed-voltage single-chip systems. The presence of high-voltage can create a situation in which the parasitic back-channel device turns on and &ldq... View full abstract»

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  • Design guidelines for optimized nested Miller compensation

    Publication Year: 2000, Page(s):97 - 102
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    The nested Miller compensation of three-stage amplifiers is reviewed by using a novel and simple design-oriented approach allowing the control of the overall phase margin as well as that of each internal loop. Furthermore, a novel technique using nulling resistors to remove the RHP zeroes is discussed which greatly improves frequency and slew-rate performance, without increasing the power consumpt... View full abstract»

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  • Cycle-domain simulator for phase-locked loops

    Publication Year: 2000, Page(s):77 - 82
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools avail... View full abstract»

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  • Free-space optics for 3D multi-chip environment

    Publication Year: 2000, Page(s):7 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    The 3D-OESP consortium is a government-industry-university collaboration dedicated to the development of the technologies required to integrate stacked silicon chips with optoelectronic devices for high-performance computing and switching applications. By utilizing the combined strengths of 3D chip packaging and optoelectronic array interconnect technologies, it is possible to bring a low-power ul... View full abstract»

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  • A novel fully integrated fan controller for advanced computer systems

    Publication Year: 2000, Page(s):191 - 194
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and ... View full abstract»

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  • Body-driving as a low-voltage analog design technique for CMOS technology

    Publication Year: 2000, Page(s):113 - 118
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included View full abstract»

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  • Use of switched buffers in very high-speed data converters

    Publication Year: 2000, Page(s):93 - 96
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    We present a new design approach for high resolution analog-to-digital converters operating at very high speeds. We show that using CMOS switches and the switched current technique are not convenient for advanced specifications. The switched buffer method proposed here offers new perspectives since it allows the designer to preserve accuracy even at high speeds of operation. The switched buffer co... View full abstract»

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  • Modeling and analysis of substrate coupled noise in pipelined data converters

    Publication Year: 2000, Page(s):125 - 130
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are inv... View full abstract»

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  • High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

    Publication Year: 2000, Page(s):135 - 140
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 μm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement View full abstract»

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  • A delta-sigma modulation based BIST scheme for mixed-signal systems

    Publication Year: 2000, Page(s):147 - 152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    We present the architecture and analysis of a built-in self-test (BIST) scheme that targets mixed-signal system-on-chip (SOC) designs. The basic idea is to employ simple yet high-tolerant digital-to-analog (DA) and analog-to-digital (AD) conversion techniques for on-chip stimulus generation and response acquisition, and to utilize on-chip programmable cores for digital signal processing required f... View full abstract»

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  • Behavioral modeling of a SONET/SDH transceiver using HDLA

    Publication Year: 2000, Page(s):73 - 76
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    In order to reduce the number of design iteration for complex mixed signal telecommunication IC's, verification through full chip simulation is a must. The objective is to verify connectivity and functionality for the whole chip including the interface between analog and digital blocks. Efficient top level simulation required the use of a mixed mode (Analog and Digital) simulator. In addition, in ... View full abstract»

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  • D/A conversion with linear-coded weights

    Publication Year: 2000, Page(s):61 - 66
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion base... View full abstract»

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  • Terabit/s optical I/O directly to VLSI chips

    Publication Year: 2000, Page(s):20 - 21
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. One such optoelectronic-VLSI (OE-VLSI) technology is based on the hybrid flip-chip area bonding of GaAs/AlGaAs multiple-quantum well (MQW) electro-absorption modulator devices directly onto active silicon CMOS circuits. The technology has reached the po... View full abstract»

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  • Sensor plane processing for multiplex imaging

    Publication Year: 2000, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Digital imaging systems are fundamentally different from analog ones because they differentiate the measurement space and the reconstruction space. Multiplex systems use this separation to optimize source reconstruction. We consider the requirements imposed on sensor plane processors by multiplex imaging systems. We consider system flexibility, analog/digital split, A/D dynamic range, bandwidth, a... View full abstract»

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  • Substrate thermal model reduction for efficient transient electrothermal simulation

    Publication Year: 2000, Page(s):185 - 190
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A multiport RC network reduction technique based on congruence transformation was developed specifically for improving the efficiency of temperature calculation in electrothermal simulations. This technique helps reduce the size of the three-dimensional lumped RC network, which is commonly used to model substrate heat conduction, while still preserving the input/output characteristics at the port ... View full abstract»

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  • A strategy for implementing dynamic element matching in current-steering DACs

    Publication Year: 2000, Page(s):51 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS cur... View full abstract»

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  • A 0.5-8.5 GHz fully-differential CMOS RF distributed amplifier

    Publication Year: 2000, Page(s):109 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    A fully-differential four-stage distributed amplifier (DA) with 5.5 dB gain and 8.5 GHz bandwidth has been integrated in 1.3 mm×2.2 mm in a 0.6 μm digital CMOS process. The DA dissipates 216 mW from a single 3 V supply. A custom CAD tool was used to optimize the DA design including device and package parasitics View full abstract»

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  • Preliminary circuits for Smart Dust

    Publication Year: 2000, Page(s):87 - 92
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper we present a miniature system that is being designed for the Smart Dust project to test the communication link and simulate basic functionality. The system includes an optical receiver to process the incoming laser signal, digital circuits to generate a pseudorandom number sequence, a corner cube reflector (CCR) to passively transmit data to the base station, and a charge pump to gen... View full abstract»

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  • CMOS DSP and microprocessor cores using optoelectronic VLSI

    Publication Year: 2000, Page(s):9 - 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    The use of inter-chip optical interconnects can lead to a dramatic increase in chip-level and system-level performance of high-performance computing and signal processing systems. In this paper, we describe our efforts to build chipsets for these applications using optoelectronic VLSI. The performance advantages of using optical interconnects are compared with the conventional approach View full abstract»

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  • Switching-induced substrate noise and mixed-signal receiver design

    Publication Year: 2000, Page(s):119 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    We use a stochastic model of the switching current to describe the power spectral density of current noise waveforms induced by digital switching events. We discuss common impedance paths, particularly arising from non-ideal properties of electronic packages, that couple this noise into the substrate of an integrated circuit. We derive estimates of the noise spectrum for modest digital power and t... View full abstract»

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  • Evaluation of the substrate noise effect on analog circuits in mixed-signal designs

    Publication Year: 2000, Page(s):131 - 134
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    This paper describes an approach used to simulate the bulk in such a way that we can evaluate the substrate noise effect on analog designs. For these simulations a simple model is used in order to reduce the time needed for the simulations. In this model we take into account the effect of the bonding wire and the bulk resistance. This simulation technique was applied to a sample and hold circuit View full abstract»

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