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Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International

Date 9-13 Feb. 2014

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Displaying Results 1 - 25 of 267
  • [Front cover]

    Page(s): 1
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  • 2014 IEEE International Solid-State Circuits Conference - Digest of Technical Papers [Copyright notice]

    Page(s): 2
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  • Table of contents

    Page(s): 3
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  • Reflections

    Page(s): 4
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  • Foreword: Silicon systems bridging the cloud

    Page(s): 5
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  • The visuals supplement and the Saratoga Group — A 25-year history

    Page(s): 6 - 7
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  • Session 1 overview: Plenary session

    Page(s): 8 - 9
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  • 1.1 Computing's energy problem (and what we can do about it)

    Page(s): 10 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (643 KB) |  | HTML iconHTML  

    Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices. View full abstract»

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  • 1.2 Cloud 2.0 clients and connectivity — Technology and challenges

    Page(s): 15 - 19
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    With the dramatically increasing use of mobile and portable devices, the need for computation has intensified, motivating the transformation of traditional static services (Web and storage) to evolve toward distributed Web services, forming Cloud 1.0; in this process, the evolution into the Smart Device Era involved many changes: stationary computing devices are going mobile, standalone devices are becoming connected, and peer-to-peer communication (email) extending to many-to-many (social networking). Two of the biggest enablers for Cloud 1.0 have been clients such as Smartphones and tablets, connected through wired and wireless networks. Embedded within each of these clients are the CPU and GPU processors needed to enable consumer applications and mobile human-interface devices (HIDs). To satisfy the ever-growing computational requirements, mobile CPU clock frequencies have extended into the GHz region. To avoid this barrier, mobile clients are driving the downscaling of process technology while motivating the rapid rise of multi-core CPUs and GPUs. In this process, new architectures involving asymmetric-CPU and octa-cores are emerging. As well, investment is pouring into the hardware/software (HW/SW) infrastructure to provide adaptive power management, thermal throttling, and efficient heterogeneous multiprocessing, all to enable maximum core usage and energy efficiency within the tight thermal limits of the Smartphone and tablet domains. View full abstract»

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  • ISSCC Awards [17 awards]

    Page(s): 20 - 21
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  • 1.3 How chips pave the Road to the Higgs particle and the attoworld beyond

    Page(s): 22 - 28
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    Scientific knowledge is the basis for new technology, but in return, new technology enables progress in science. One example has been the introduction of semiconductor imagers in astronomy. Telescopes now can go into space, taking stunning pictures and opening up new wavelength windows. Another example will be described in this paper. In the field of elementary particle physics, the experiments at the Large Hadron Collider (LHC) at CERN use custom-designed CMOS chips as key components for the analog signal processing and digital information extraction, and these chips enabled significant discoveries to be made, that of the Higgs particle in particular, after only a few years of operation. View full abstract»

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  • 1.4 The next generation of networked experiences

    Page(s): 29 - 35
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    The evolution of networking technology has enabled impressive networked experiences, ranging from connected mobile context-aware experiences to immersive experiences provided by large-screen interactive displays. The rapid pace of innovation and trends in consumerization have made these experiences affordable and widely available, greatly increasing end users' expectations. In the years ahead, networks will undergo the greatest architectural transition seen in the past two decades, with the advent of software-defined networking (SDN) and the Internet of things (IoT). By taking an experience-driven approach to this architectural shift, we can understand the requirements for the underlying compute and network infrastructure, client devices, and sensors and the interaction of applications with the network. This paper discusses the next generation of networked experiences. View full abstract»

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  • Session 2 overview: Ultra-high-speed transceivers and techniques: Wireline subcommittee

    Page(s): 36 - 37
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  • 2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

    Page(s): 38 - 39
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    A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points. View full abstract»

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  • 2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS

    Page(s): 40 - 41
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    Network traffic speeds are increasing to meet the demands of data centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that remains is the high power consumption of 100Gb/s systems. As mentioned in [1], power dissipation of the 100GbE gearbox transceiver is a significant portion of the optical module power. This paper demonstrates a low-power quad-lane 20-to-28Gb/s transceiver targeting 100GbE/40GbE (IEEE 802.3ba) standard. The transceiver features a low-jitter TX, half-rate calibrated RX slicer with folded active inductor and a wide-range PLL (20 to 28GHz) with low-power half-rate clock driver using programmable distributed inductors. It operates from a standard 0.9V supply and the power consumption for line-side transceiver is 780mW for 28Gb/s. Additionally the chipset integrates a system interface that is CAUI-compliant, composed of a 10-lane data bus operating at 9.95 to 11.2Gb/s. In default mode it converts 100GbE (10×10 Gb/s) signal to a 4×25Gb/s line signal and vice versa. The line-side interface can also be reconfigured as 40GbE, with both line- and system-side operating at 4×11.2Gb/s. View full abstract»

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  • 2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

    Page(s): 42 - 43
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    Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead. View full abstract»

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  • 2.4 A 25Gb/s 5.8mW CMOS equalizer

    Page(s): 44 - 45
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    The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer, and the front-end equalizer. The use of charge-steering techniques has shown promise for the low-power implementation of the first two functions [1]. This paper introduces a half-rate 25Gb/s equalizer employing charge steering and achieving an efficiency of 0.232mW/Gb/s. View full abstract»

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  • 2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS

    Page(s): 46 - 47
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    In this work, a DFE is presented that is designed specifically to operate at low VDD and scale well in energy-efficiency. To achieve this goal, the following innovations are introduced: 1) fast and energy-efficient charge-based latch and sample-and-hold (S/H) topologies; 2) a CMOS-clocked quarter-rate DFE architecture with summer gain and power optimization; 3) an integrating summer with a compact common-mode restoration circuit. Leveraging these techniques, the DFE is capable of operating at or below 0.7V, with an energy efficiency of or better than 0.25pJ/bit. View full abstract»

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  • 2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface

    Page(s): 48 - 49
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    Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, and large display size. Since CES embeds the clock-transition information in the data stream, it enables wide-range clock acquisition with PLL-based [1,2] or DLL-based [3-5] clock-and-data recovery (CDR) schemes. It also offers additional benefits of reduced EMI and low cost by eliminating the need for an additional clock channel or reference signal. For clock recovery, however, CES transmits a significant number of extra bits attached to each data packet to carry clock transition information. The number of extra bits is at least three [4] or four [3], sufficient to reduce the effect of inter-symbol interference (ISI) on clock transitions from adjacent random data patterns, providing cleaner reference to the clock recovery circuit. The repeated transitions in every data packet also intensify the spectral energy at the clock frequency as the data-rate increases, seriously aggravating EMI problem. This paper presents a DLL-based CDR with a new CES scheme that carries clock transitions with only one bit overhead but effectively sees the same ISI as a three- or four-bit overhead. By introducing a pattern-dependent clock embedding, our CES assimilates with random data transitions and almost eliminates the EMI issue. The CDR, implemented in 65nm CMOS, shows a lock range of 6.5 to 9Gb/s and a power efficiency of 0.63mW/Gb/s at 9Gb/s. View full abstract»

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  • 2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology

    Page(s): 50 - 51
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    This paper presents a 4-tap coefficient-error-robust feed-forward equalization (FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data transmission with a limited power budget. However, calibration overhead for thousands I/Os to compensate coefficient errors due to nano-scale variation has a high hardware cost. To reduce this overhead, we develop a coefficient-error-robust FFE (B-FFE) TX architecture that uses the channel loss to suppress eye perturbation due to coefficient errors while behaving identically to a conventional FFE. View full abstract»

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  • 2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

    Page(s): 52 - 53
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    High-speed transceivers embedded inside FPGAs require software-programmable clocking circuits to cover a wide range of data rates across different channels [1]. These transceivers use high-frequency PLLs with LC oscillators to satisfy stringent jitter requirements at increasing data rates. However, the large area of these oscillators limits the number of independent LC-based clocking sources and reduces the flexibility offered by the FPGA. A ring-based PLL occupies smaller area but produces higher jitter. With injection-locking (IL) techniques [2-3], ring-based oscillators achieve comparable performance with their LC counterparts [4-5] at frequencies below 10GHz. Moreover, addition of a PLL to an injection-locked VCO (IL-PLL) provides injection-timing calibration and frequency tracking against PVT [3,5]. Nevertheless, applying injection-locking techniques to high-speed ring oscillators in deep submicron CMOS processes, with high flicker-noise corner frequencies at tens of MHz, poses a design challenge for low-jitter operation. Shown in Fig. 2.8.1, injection locking can be modeled as a single-pole feedback system that achieves 20dB/dec of in-band noise shaping against intrinsic VCO phase noise over a wide bandwidth [6]. As a consequence, this technique suppresses the 1/f2 noise of the VCO but not its 1/f3 noise. Note that the conventional IL-PLL is capable of shaping the VCO in-band noise at 40dB/dec [6]; however, its noise shaping is limited by the narrow PLL bandwidth due to significant attenuation of the loop gain by injection locking. To achieve wideband 2nd-order noise shaping in 20nm ring oscillators, we present a circuit technique that applies pulse-position-modulated (PPM) injection through feedback control. View full abstract»

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  • 2.9 A Background calibration technique to control bandwidth in digital PLLs

    Page(s): 54 - 55
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    The bandwidth of a phased-locked loop (PLL) is dependent on several analog parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends on the gains of two mixed-signal building blocks, namely the time/digital converter (TDC) and the digitally-controlled oscillator (DCO), that have conversion characteristics that are not well-controlled. The situation is even more cumbersome employing a singlebit TDC, often referred to as bang-bang phase detector (BBPD), where the linearized gain is inversely proportional to the input jitter [1]. An accurate and repeatable value of the PLL bandwidth, and in the general of the frequency response, is essential to meet several specifications, such as stability margin, settling time, jitter and spur level. When the PLL is operated as a direct frequency modulator with pre-emphasis of the modulation signal, the accuracy requirement of the frequency response is even more demanding [2]. Previously disclosed methods to control PLL bandwidth require a modulation signal to be injected into the loop [2], compensate the gain variations of just a single block (e.g., VCO [3] or BBPD [4]), or operate in the foreground [5]. This paper presents a digital PLL employing a digital background normalization of loop gain, which makes it independent of any analog variable (except for the reference frequency, which often is available from an accurate source). This method requires no injection of additional test signals and operates at a low rate, achieving low-noise and low-power operation, and also is suitable even for bangbang PLLs. View full abstract»

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  • Session 3 overview: RF techniques: RF subcommittee

    Page(s): 56 - 57
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  • 3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier

    Page(s): 58 - 59
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    One of the ultimate goals in power amplifier design is to enhance the effective efficiency and achieve a long battery life. Therefore, both the peak efficiency and the efficiency loss due to antenna impedance mismatch or power back-off are highly critical design issues. In particular, the challenge of the antenna impedance mismatch is becoming more severe, due to the increased frequency band and smaller antenna size. Moreover, the antenna mismatch also changes with time due to the user proximity effect [1]. View full abstract»

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  • 3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

    Page(s): 60 - 61
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    In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further improve the power efficiency over ET by replacing the linear PA with a switching PA driven by a phase signal [7]. However, to meet the specified low distortion, especially for LTE with a wide bandwidth baseband signal, an EER PA generally has difficulty achieving a wide bandwidth for the phase signal path, and requires a high-speed supply modulator, and highly accurate timing between envelope and phase signals. To overcome these problems, this paper introduces an envelope / phase generator based on a mixer and a timing aligner based on a delay-locked loop. Additionally, they were integrated with a switching PA and a supply modulator on the same die. View full abstract»

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