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SOC Conference (SOCC), 2013 IEEE 26th International

Date 4-6 Sept. 2013

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Displaying Results 1 - 25 of 75
  • [Front cover]

    Page(s): c1
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  • Message from conference general chair

    Page(s): 4 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB) |  | HTML iconHTML  

    On behalf of the Organizing Committee, I welcome you to the 26th IEEE International System-on-Chip (SOC) Conference (SOCC 2013), held this year at the Fraunhofer IIS in Erlangen, Germany. View full abstract»

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  • Message from program chairs

    Page(s): 6
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    On behalf of the Technical Program Committee (TPC), it is our pleasure to welcome you to the 26th IEEE International System-on-Chip Conference (SOCC 2013). The goal of the conference is to continue to present and disseminate state of the art research and development from both academia and industry sectors supporting the wide-ranging industries in both manufacturing and applications. View full abstract»

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  • Program-at-a glance

    Page(s): 7 - 8
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  • 2013 SOCC organizing committee

    Page(s): 9
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  • 2013 technical program committee

    Page(s): 10 - 11
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  • List of reviewers

    Page(s): 12
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  • Table of contents

    Page(s): 13 - 23
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  • Author index

    Page(s): 24 - 26
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  • Keynote speaker: “The roadway to innovation”

    Page(s): 29
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    Summary form only given. Electronic innovation is becoming increasingly more important in the evolution of our society. Noble goals of extending healthy lives with improving medical capabilities, creating a cleaner environment, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges driving a strong need for integration of disparate functional blocks and exponential scaling of content. A central focus in this evolution is the automobile. Emission standards are driving systems from single core, simple computational units to highly integrated, scaled out, safe and secure domain controllers, which host multiple diverse software environments. Shifts toward autonomous driving are leading to integrated sensing systems leveraging advanced algorithms for detection classification and safe decision making. The strong demand for connected vehicles is resulting in revolutionary changes to the vehicle network and communication infrastructure embedded in the automobile. We will explore how these automotive trends translate to future challenges for technology platforms, integrated circuit module development, system-on-chip integration, design of safe systems, and implementation of secure but diagnosable systems. View full abstract»

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  • Plenary speaker: “The pig in the poke? - Strategies to avoid unpleasant surprises with IP on your SoC”

    Page(s): 30
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    Developing an SoC and meeting the profitable market window just requires the intense use of pre-verified functional blocks, either “homegrown” or coming from external IP providers. The fast growing 3rd party IP market place is the direct consequence of this. While we can see significant changes in the kind of IP and its distribution models over time, the main concerns of an SoC designer remains the same: Will the IP work as anticipated, and how much time can I really save by using such a “Lego building brick” rather than developing the functionality from scratch? The talk will briefly compare the IP market and its maturity with the EDA market and address the change of requirements to IP over time. The trend towards next gen IP demands will be addressed. From this background the author will share important learnings to help users avoid the most common pitfalls when designing-in the IP into their next complex SoC. View full abstract»

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  • Plenary speaker: “Visions of future SoC design: Why heterogeneous architectures and power matter”

    Page(s): 31
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    Summary form only given. SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, total power consumption has been and is a challenge moving forward as SoCs keep increasing in performance and functionality whilst users shift from mains powered appliances to the use of battery driven equipment. The presentation therefore discusses some of these challenges and shows examples of how said challenges have been and will be addressed moving forward. Understanding technological and market trends and their drivers in key segments determine the ability to successfully translate vision into reality, and to constantly enhance it. The presentation further touches upon key functional blocks in modern SoCs and explains how the GPU is becoming the new driving force not only for modern applications but also for design methodologies and process technologies, and how heterogeneous processing is transforming the way SoCs handle key user applications such as UI's, gaming, multimedia and more. View full abstract»

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  • Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

    Page(s): 33 - 36
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    The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue. View full abstract»

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  • An optimal design of a fault tolerant reversible multiplier

    Page(s): 37 - 42
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    One of the most challenging issues in circuit design is power consumption. Reversible logic is one of the ways for power optimization. In this paper, we propose an optimal design of a fault tolerant reversible n×n multiplier circuit, where n is the number of bits of the operands of multiplier. Two algorithms have been presented to construct the Partial Product Generation (PPG) circuit and the Multi-Operand Addition (MOA) circuit of the proposed multiplier. We also propose a new fault tolerant reversible gate, namely, LMH gate, to produce an optimal multiplier. In addition, several theorems on the numbers of gates, garbage outputs and quantum cost of the fault tolerant reversible multiplier have been presented to show its optimality. The comparative study shows that the proposed design is much better than the existing approaches considering all the efficiency parameters of reversible logic design which includes numbers of gates, garbage outputs, quantum cost and constant inputs; e.g., for a 4×4 multiplier, the proposed design achieves the improvement of 26.32% in terms of number of gates, 12.5% in terms of garbage outputs, 17% in terms of quantum cost and 20.97% in terms of constant inputs over the existing latest approach. View full abstract»

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  • Layout regularity metric as a fast indicator of high variability circuits

    Page(s): 43 - 48
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    Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Layout regularity is one of the trending techniques suggested by design for manufacturability (DFM) to mitigate process variations effect. However, there is no study relating either lithography or electrical variations to layout regularity. In this paper, a novel method is presented to model electrical variations due to systematic lithographic variations. Then, geometrical-based layout regularity metric was derived; this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The metric results compared to the electrical variability model results show matching percentage that can reach 80%. Calculation of the metric takes only few minutes on 1 mm × 1 mm. View full abstract»

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  • Architecture and circuit design of parallel processing elements for de novo sequence assembly

    Page(s): 50 - 54
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    In this paper, we purpose a hardware-compatible parallel DNA de novo sequence assembly algorithm. The k-mers and contigs are stored in different processing elements (PE) according to their leading bases, and assembled through exchanging the head/tail information packets between PEs. Unlike conventional de Bruijn graph approaches, our algorithm does not need to save complete graphs, thus it is better for hardware implementation. The PE circuit is implemented. Simulation results show that the solution qualities are comparable to conventional software approaches. View full abstract»

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  • UWB receiver for breast cancer detection: Comparison between two different approaches

    Page(s): 55 - 60
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    In UWB imaging for breast cancer detection, breast-reflected RF signals are processed to create energy images. This method was validated with instrumentation tools, which must be replaced with integrated circuits. We compare two front-end architectures, Direct Conversion (DC) and Coherent Equivalent Time Sampling (CETS). We evaluate the effect-on energy maps and SCR/SMR metrics-of noise sources, phase inaccuracies and non-linearity. DC receiver is more sensitive to phase inaccuracies and so less robust than CETS receiver. The latter can work in time domain with UWB pulses, other than in frequency domain like the DC one, which reduces acquisition time without performance impact. View full abstract»

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  • A new data acquisition design for breast cancer detection system

    Page(s): 61 - 66
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    Modern mammography screening for breast cancer detection adopted computed tomography techniques and multi-dimensional (i.e. 3D or 4D) Tomosynthesis to improve cancer detection rate. These new trends demand novel SoC designs that can accommodate the increasing volume of raw data from multi-dimensional (i.e. 3D or 4D) Tomosynthesis with comparable X-ray dose. The current paper introduces two core technologies: Adaptive Digital Estimator (ADE) and Self-detecting sensory array based on Compressive Sensing (CS) concept and inter-reset sampling techniques. First of its kind, the new designs can simultaneously achieve high speed data acquisition and reduce data amount by an average of 40%. View full abstract»

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  • A 72dBO 11.43mA novel CMOS regulated cascode TIA for 3.125Gb/s optical communications

    Page(s): 68 - 72
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    This paper presents the design of a 3.125Gbps CMOS transimpedance amplifier (TIA) with a novel regulated cascode (RGC) preamplifier. The proposed RGC circuit isolates the large input parasitic capacitance and then improves the bandwidth limitation. This TIA was fabricated in 1P6M 0.18um CMOS process and consumes 11.43mA from 1.8V supply voltage. The TIA achieves a gain of 72dBΩ and 2.4GHz bandwidth when connected to a 0.5pF photodiode. View full abstract»

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  • PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks

    Page(s): 73 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    The implementation of a wireless sensor mote as a system on chip (SoC) enables the energy consumption to be decreased substantially by using dedicated hardware accelerators. This work combines an efficient prediction model with a Kalman filter (PKF) to reduce the communication cost in Wireless Sensor Networks (WSNs) with a guaranteed data quality. The hardware accelerator requires fewer resources than previous approaches, while achieving higher energy reductions. Exhaustive experimental results based on datasets from a real WSN application confirm the advantages of the proposed mechanism. View full abstract»

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  • A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control

    Page(s): 79 - 82
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    This paper presents a burst-mode equalizer for the communication incorporating electrical idle state which is usually used for power management. Fabricated in 0.18μm CMOS technology, the proposed equalizer can compensate over 90-inch microstrip on an FR4 PCB, which has a 40dB loss at 3GHz. The proposed overshoot control scheme with reference calibration can reduce offset-induced error on detections and is observed to achieve jitter improvement of 0.06UI. With the help of envelope detector and digital adaptation, the reaction time under burst-mode transmission is 5.5ns or 33bit-time. The equalizer consumes 26.7mW from a 1.8V supply and measured BER is less than 10-12. View full abstract»

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  • Adaptive driver with automatic sense and calibration in CMOS 40LP

    Page(s): 83 - 86
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    Dynamically calibrated driver block is presented which automatically adapts its termination resistance to the channel's impedance. The driver senses the channel and calibrates to its characteristic impedance anywhere between 30 - 120 ohms. This circuit functions successfully for a minimum propagation delay of 500 ps on the channel. Results on the STM CMOS 40LP process confirm the driver's impedance match to that of the line with an accuracy of +/- 8% with +/-3σ variation in the process, +/- 10% voltage spread at 2.5V and temperature variation range of - 40 to 125 degrees centigrade. View full abstract»

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  • Sub-10 µW CMOS wake-up receiver IP for green SoC designs

    Page(s): 88 - 91
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    Minimizing waste of resources by reduction of battery replacements in mobile smart objects gives an electronic system a green attribute. Wireless communication is mandatory for modern smart systems. As the receiver's power consumption dominates the total power budget, novel power reduction techniques are recommended. This paper proposes an ultra-low power UHF wake-up receiver IP in a 130 nm CMOS technology. The power consumption is scalable between 3 μW and 28 μW. In contrast to common polling receivers with reaction times of more than 1 second, this novel fully integrated 868 MHz wake-up receiver depicts reaction times between 30 ms and 484 ms. The core size is 1.0 mm2. The sensitivity is -83 dBm. Adding such an ultra-low power IP to a SoC circuit, a quick radio interface for remote access on demand is provided and enables a broad variety of innovative applications: remote sensor readout, wireless body area networks, wireless authentification, localisation and asset tracking in logistics and health-care. View full abstract»

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  • A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range

    Page(s): 92 - 97
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    In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to super-threshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781ps, a setup time of - 610ps, and a power dissipation of 2.3μW when the input voltage is 0.4V. View full abstract»

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  • An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

    Page(s): 98 - 103
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    Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents the design of an optimal reversible fault tolerant carry look-ahead adder. We present an algorithm to design a generalized n-bit carry look-ahead adder, where n is the number of bits of the operands. A new technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. In addition, several theorems on the numbers of garbage outputs, quantum cost, quantum gate complexity and delay of the fault tolerant reversible carry look-ahead adder have been presented to show its optimality. Simulation using Microwind DSCH software has been shown to verify the correctness of the function of the proposed carry look-ahead adder. The comparative study shows that the proposed design is much better than the existing approach considering all the efficiency parameters of reversible circuit design which includes numbers of gates, quantum cost, delay, quantum gate complexity and garbage outputs. The proposed 8-bit reversible fault tolerant carry look-ahead adder improves 94.9% on the number of gates, 92.4% on the quantum cost, 93.2% on the garbage outputs and 14.5% on the delay than the existing design. View full abstract»

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