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SOC Conference (SOCC), 2013 IEEE 26th International

Date 4-6 Sept. 2013

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Displaying Results 1 - 25 of 75
  • [Front cover]

    Publication Year: 2013, Page(s): c1
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  • Message from conference general chair

    Publication Year: 2013, Page(s):4 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB) | HTML iconHTML

    On behalf of the Organizing Committee, I welcome you to the 26th IEEE International System-on-Chip (SOC) Conference (SOCC 2013), held this year at the Fraunhofer IIS in Erlangen, Germany. View full abstract»

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  • Message from program chairs

    Publication Year: 2013, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    On behalf of the Technical Program Committee (TPC), it is our pleasure to welcome you to the 26th IEEE International System-on-Chip Conference (SOCC 2013). The goal of the conference is to continue to present and disseminate state of the art research and development from both academia and industry sectors supporting the wide-ranging industries in both manufacturing and applications. View full abstract»

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  • Program-at-a glance

    Publication Year: 2013, Page(s):7 - 8
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  • 2013 SOCC organizing committee

    Publication Year: 2013, Page(s): 9
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  • 2013 technical program committee

    Publication Year: 2013, Page(s):10 - 11
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  • List of reviewers

    Publication Year: 2013, Page(s): 12
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  • Table of contents

    Publication Year: 2013, Page(s):13 - 23
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  • Author index

    Publication Year: 2013, Page(s):24 - 26
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  • Keynote speaker: “The roadway to innovation”

    Publication Year: 2013, Page(s): 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    Summary form only given. Electronic innovation is becoming increasingly more important in the evolution of our society. Noble goals of extending healthy lives with improving medical capabilities, creating a cleaner environment, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are bein... View full abstract»

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  • Plenary speaker: “The pig in the poke? - Strategies to avoid unpleasant surprises with IP on your SoC”

    Publication Year: 2013, Page(s): 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (90 KB) | HTML iconHTML

    Developing an SoC and meeting the profitable market window just requires the intense use of pre-verified functional blocks, either “homegrown” or coming from external IP providers. The fast growing 3rd party IP market place is the direct consequence of this. While we can see significant changes in the kind of IP and its distribution models over time, the main concerns of a... View full abstract»

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  • Plenary speaker: “Visions of future SoC design: Why heterogeneous architectures and power matter”

    Publication Year: 2013, Page(s): 31
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Summary form only given. SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, total power consumption has been and is a challenge moving forward as SoCs keep increasing in performance and functionality whilst users shift from main... View full abstract»

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  • Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

    Publication Year: 2013, Page(s):33 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1628 KB) | HTML iconHTML

    The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD... View full abstract»

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  • An optimal design of a fault tolerant reversible multiplier

    Publication Year: 2013, Page(s):37 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1677 KB) | HTML iconHTML

    One of the most challenging issues in circuit design is power consumption. Reversible logic is one of the ways for power optimization. In this paper, we propose an optimal design of a fault tolerant reversible n×n multiplier circuit, where n is the number of bits of the operands of multiplier. Two algorithms have been presented to construct the Partial Product Generation (PPG) circuit and t... View full abstract»

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  • Layout regularity metric as a fast indicator of high variability circuits

    Publication Year: 2013, Page(s):43 - 48
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (863 KB) | HTML iconHTML

    Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Layout regularity is one of the trending techniques suggested by design for manufacturability (DFM) to mitigate process variations effect. However, there is no study relating either lithography or electrical variations to layout regularity. In this paper, a... View full abstract»

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  • Architecture and circuit design of parallel processing elements for de novo sequence assembly

    Publication Year: 2013, Page(s):50 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (973 KB) | HTML iconHTML

    In this paper, we purpose a hardware-compatible parallel DNA de novo sequence assembly algorithm. The k-mers and contigs are stored in different processing elements (PE) according to their leading bases, and assembled through exchanging the head/tail information packets between PEs. Unlike conventional de Bruijn graph approaches, our algorithm does not need to save complete graphs, thus it is bett... View full abstract»

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  • UWB receiver for breast cancer detection: Comparison between two different approaches

    Publication Year: 2013, Page(s):55 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1682 KB) | HTML iconHTML

    In UWB imaging for breast cancer detection, breast-reflected RF signals are processed to create energy images. This method was validated with instrumentation tools, which must be replaced with integrated circuits. We compare two front-end architectures, Direct Conversion (DC) and Coherent Equivalent Time Sampling (CETS). We evaluate the effect-on energy maps and SCR/SMR metrics-of noise sources, p... View full abstract»

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  • A new data acquisition design for breast cancer detection system

    Publication Year: 2013, Page(s):61 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1227 KB) | HTML iconHTML

    Modern mammography screening for breast cancer detection adopted computed tomography techniques and multi-dimensional (i.e. 3D or 4D) Tomosynthesis to improve cancer detection rate. These new trends demand novel SoC designs that can accommodate the increasing volume of raw data from multi-dimensional (i.e. 3D or 4D) Tomosynthesis with comparable X-ray dose. The current paper introduces two core te... View full abstract»

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  • A 72dBO 11.43mA novel CMOS regulated cascode TIA for 3.125Gb/s optical communications

    Publication Year: 2013, Page(s):68 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1808 KB) | HTML iconHTML

    This paper presents the design of a 3.125Gbps CMOS transimpedance amplifier (TIA) with a novel regulated cascode (RGC) preamplifier. The proposed RGC circuit isolates the large input parasitic capacitance and then improves the bandwidth limitation. This TIA was fabricated in 1P6M 0.18um CMOS process and consumes 11.43mA from 1.8V supply voltage. The TIA achieves a gain of 72dBΩ and 2.4GHz b... View full abstract»

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  • PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks

    Publication Year: 2013, Page(s):73 - 78
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB) | HTML iconHTML

    The implementation of a wireless sensor mote as a system on chip (SoC) enables the energy consumption to be decreased substantially by using dedicated hardware accelerators. This work combines an efficient prediction model with a Kalman filter (PKF) to reduce the communication cost in Wireless Sensor Networks (WSNs) with a guaranteed data quality. The hardware accelerator requires fewer resources ... View full abstract»

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  • A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control

    Publication Year: 2013, Page(s):79 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2095 KB) | HTML iconHTML

    This paper presents a burst-mode equalizer for the communication incorporating electrical idle state which is usually used for power management. Fabricated in 0.18μm CMOS technology, the proposed equalizer can compensate over 90-inch microstrip on an FR4 PCB, which has a 40dB loss at 3GHz. The proposed overshoot control scheme with reference calibration can reduce offset-induced error on de... View full abstract»

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  • Adaptive driver with automatic sense and calibration in CMOS 40LP

    Publication Year: 2013, Page(s):83 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1065 KB) | HTML iconHTML

    Dynamically calibrated driver block is presented which automatically adapts its termination resistance to the channel's impedance. The driver senses the channel and calibrates to its characteristic impedance anywhere between 30 - 120 ohms. This circuit functions successfully for a minimum propagation delay of 500 ps on the channel. Results on the STM CMOS 40LP process confirm the driver's impedanc... View full abstract»

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  • Sub-10 µW CMOS wake-up receiver IP for green SoC designs

    Publication Year: 2013, Page(s):88 - 91
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1274 KB) | HTML iconHTML

    Minimizing waste of resources by reduction of battery replacements in mobile smart objects gives an electronic system a green attribute. Wireless communication is mandatory for modern smart systems. As the receiver's power consumption dominates the total power budget, novel power reduction techniques are recommended. This paper proposes an ultra-low power UHF wake-up receiver IP in a 130 nm CMOS t... View full abstract»

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  • A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range

    Publication Year: 2013, Page(s):92 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1423 KB) | HTML iconHTML

    In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock ... View full abstract»

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  • An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

    Publication Year: 2013, Page(s):98 - 103
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1169 KB) | HTML iconHTML

    Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents the design of an optimal reversible fault tolerant carry look-ahead adder. We present an algorithm to design a generalized n-bit carry look-ahead adder, w... View full abstract»

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