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Electronic Packaging Technology (ICEPT), 2013 14th International Conference on

Date 11-14 Aug. 2013

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Displaying Results 1 - 25 of 295
  • [Front cover]

    Page(s): 1
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  • [Copyright notice]

    Page(s): 1 - 2
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  • Table of contents

    Page(s): 1 - 22
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  • Author index

    Page(s): 1 - 18
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  • Solder behavior and defect formation in joining process by Al/Ni self-propagating reaction

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (894 KB) |  | HTML iconHTML  

    Joining methods based on self-propagating reaction have been presented in the field of electronic packaging to solve the mismatch of CTEs (Coefficient of thermal expansion) among materials. As a key factor for joining reliability, the defects should be minimized to obtain the sound and reliable solder joints. However, due to the very fast heating and cooling speeds, the solder behavior and the formation mechanism of defects in self-propagating joining are different from that in traditional joining methods. In this study, the interfacial IMC morphology, defects in joints and the fracture behavior had been characterized to enable an analysis and evaluation of the solder behavior and formation of defects in self-propagating joints. In addition, the influence of material properties, applied pressure and ambient temperature had been investigated which can assist further optimization of process and the joining quality. View full abstract»

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  • Stud bump process for flip-chip research: Improve UPH of stud bump

    Page(s): 6 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    A-03 Flip-Chip in Chip card is a kind of new technology applied widely in the semiconductor field. It is becoming a big challenge for the stud bump on the wafer due to smaller and smaller bond pad, consequently smaller bump size with more stable process control becomes very critical due to UPH (Units Per Hour) dropped greatly. In this paper, the process of stud bump is briefly introduced and key requirements are defined. The common mechanism of different stud bump modes is clarified with process procedure. By comparison of different stud bump modes, these main issues in manufacturing line can be addressed by 6 sigma methodology. Then the key factors are filtered by DoE experiments. After that, data validation is performed based on the results of Box plot of CEAD software. The optimized process parameters are drilled for mass production to achieve higher and stable UPH. The whole evaluation can be finalized by data analysis. View full abstract»

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  • High speed test structures for in-line process of 3D system in packaging

    Page(s): 11 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    As the requirement of portable and smart devices rapidly increasing, applications of high performance 3D integration and M/NEMS packaging have enormous market potential. High speed in-line testing is a critical bottleneck for 3D SiP and TSV processes. In this paper, we promote a method of in-line testing for interconnection performance of TSV structures, and a novel 3D CPW model for performance testing is introduced. The S parameters and Z parameters are simulated respectively. To determine the optimum TSV diameter and sidewall thickness, different types of the model have been analyzed. During our experiments, a typical structure for high frequency performance testing was fabricated successfully. The results were compared with related simulations. By using this method, the high frequency performance testing of TSV can be achieved. View full abstract»

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  • Wafer level package of Wideband Microwave Transmission System and Integrated Microwave Antenna using BCB/Metal structure with the die embedded in Si substrate

    Page(s): 16 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (862 KB) |  | HTML iconHTML  

    In this paper, a wafer-level package for a microwave transmission system has been implemented and tested. Three Monolithic Microwave Integrated Circuits (MMICs) packaged in one microwave system are first proposed. The packaged system consists of an up-converter, a drive amplifier and a power amplifier. All the modules are embedded in the cavities pre-etched in a low-resistivity silicon (Si) substrate. BCB layers are coated on the components and silicon substrate, serving as interlayer dielectrics (ILDs). Also, a technique for micro-strip patch antenna and folded slot antenna fabricated using BCB as dielectric was presented. The most distinctive feature of this technique is that the antenna is integrated in low resistive silicon wafer and completely compatible with the microwave multi-chip module (MMCM) packaging process. The electrical properties of the packaging structure are investigated. The measured transmission characteristics of the packaged system shows that the modules can work at very wide band, at the range of 6-18GHz (X/Ku band) and its gain agrees well with the theoretical results. The two antennas resonate at 14.9 GHz with 1.59% impedance bandwidth and 15.6 GHz with 14.7% impedance bandwidth, respectively. View full abstract»

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  • Fabricating processes of free-standing silicon nitride thin film for MEMS devices

    Page(s): 23 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (681 KB) |  | HTML iconHTML  

    In this paper, experiments were carried out to fabricate a kind of free-standing silicon nitride thin film which was applied to many MEMS devices, especially for the gas flow sensors and Pirani. A series of manufacturing processes were researched and optimized to obtain perfect experimental results. LPCVD silicon nitride, dry etching silicon nitride and wet etching silicon were carefully studied in the experiments.1 um thick SiN layer was deposited on the double-sides polished silicon wafer. ICP was employed to obtain the corrosion windows. Results showed that etching rates of the SiN and Si are 0.17 um/min and 1.18 um/min respectively. Wet etching process with the conditions of 30% KOH solution at 85°C was applied to release the SiN films from the substrate. Wet etching rate was about 0.817 um/min. The chromium (50nm) and platinum (200nm) layers were sputtered onto the SiN layer which acted as resistances in the test circuits. Finally, many ideal metallized free-standing silicon nitride films were fabricated on the single wafer surface. Without doubt, it may have a long-term positive impact on MEMS development and applications. View full abstract»

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  • Fabrication and measurement of Si-based inductors integrated in WLP

    Page(s): 27 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    Nowadays, inductors are prone to be integrated into chip surface for miniaturization considerations in some RF applications, but high Q factor cannot be achieved because of the lossy CMOS Si substrate. In this study, single layer spiral coils of one turn were fabricated on Si wafers with high and low resistivity via redistribution process and a polyimide layer were added on the wafer with low resistivity to reduce the substrate losses. The inductors were tested by vector network analyzer and the Q factors were compared. The highest Q factor was achieved on the wafers with high resistivity. The polyimide insulation layer can reduce the substrate loss effectively and making better Q factor. View full abstract»

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  • Failure of chip sized packaging (CSP) under coupling fields of electrical current and thermal cycle

    Page(s): 30 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB) |  | HTML iconHTML  

    In this work, we investigated the failure behavior of a commercial chip size packaging (CSP) under coupling fields of electrical current and thermal cycles. The failure process was real-time monitored through the response resistance change. Under the coupling condition, the lifetime was much shorter than that in single thermal cycle condition. Instead of the void accumulation mechanism, the excessive Joule heat was considered to be failure mechanism in coupling condition. The high temperature induced rapid dissolution of Cu UBM and overheat led to the melt of the solder. View full abstract»

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  • A novel package-on-package stacking technique

    Page(s): 34 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (623 KB) |  | HTML iconHTML  

    In this paper a four-layer package-on-package(PoP) stacking structure was introduced which allowed the whole package using fine pitch solder ball and consequently improved the interconnection I/O density between the neighboring packages. View full abstract»

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  • Research on testing of a microsystem based on SiP

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    System in Package (SiP) technology satisfies the further increasing demand by integration of different functions into one unit to reduce size and improve functionality. But the disadvantages of SiP are also increased risks in reliability, manufacturability, and difficulty with test access. A complete final test is necessary before its application. This paper presents a functional test scheme for a mircosystem based on 3D-SiP. Test system consists of a test board designed specifically and Cygwin environment of PC in debug support unit (DSU) and JTAG TAP techniques. It allows the complete final system-testing carry out in a fast, flexible, and nondestructive way. And it can improve the testability and reliability of microsystem. View full abstract»

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  • Design of test structures for electrical and reliability measurements in a 2.5D TSV interposer

    Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1075 KB) |  | HTML iconHTML  

    A 2.5D three-dimensional (3D) silicon interposer with through silicon vias (TSV) was designed and fabricated. All structures are for the purpose of evaluating the design and layout, electrical testing, and to evaluate process reliability of the 2.5D interposer. Three levels are tested: chip, interposer and plastic substrate. The paper details the layout of the three levels, the principal electrical tests and extraction of TSV parameters such as the resistance of TSVs pads and lines. The design structure also tests the reliability of the 2.5D package structure by thermal stressing. The electrical test results are discussed in relation to applicability at high frequencies. View full abstract»

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  • Vacuum fluid charging and packaging technique for micro heat pipes

    Page(s): 46 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (519 KB) |  | HTML iconHTML  

    One of the most critical issues in electronic industry is the thermal management of electronic devices, such as high-power light-emitting diodes (LEDs), high density integrated circuit(IC). Currently, the major limitation for the development of such devices is due to the lack of an efficient technique to remove heat in a narrow space. Micro heat pipes (MHPs) using MEMS technique can solve this problem theoretically. However, the charge of working fluid in such a small volume is still unsolved. Unfortunately, the performance of MHPs largely depends on the accuracy of filling ratio. Double air pumping charge method is proposed in this paper. The first air pumping process made the working fluid flow into the chamber of MHPs, the second pumping ensure the final filling ratio and the vacuum degree. This method can reach high accuracy filling and high vacuum for MHP. Meanwhile, the charge and package system is simple and has the potential to mass production. View full abstract»

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  • Improved EBG structure used torestrain simultaneous switching noise

    Page(s): 50 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    With the trend development of the high speed electronic circuits and miniaturization, The simultaneous switching noise (SSN) of power /ground plane become a major bottleneck for high speed design. The existing method of suppressing SSN has their shortcomings. Based on the equivalent circuit analysis for classic electromagnetic band gap (EBG) structure, the new structure in improving the bandwidth is proposed, Electromagnetic simulation verified that the improved electromagnetic band gap structure can effectively restrain the electromagnetic noise in a wide frequency, which provides methods to improve the narrow bandwidth of EBG. View full abstract»

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  • Effectively restrain the synchronous switch noise through attaching EBG and capacitor

    Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    With the decrease of the digital circuit noise tolerance and the timing margins tolerance. The simultaneous switching noise (SSN) of Power ground plane become a major bottleneck for high speed design. The existing method of suppressing SSN exist their short comings. In this paper, the new method combined electromagnetic band gap (EBG) with decoupling capacitors is put forwarded to use design to suppress SSN, the software simulation results show that the method is effective. View full abstract»

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  • Flip chip assembly with advanced RDL technology

    Page(s): 57 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    With silicon node technology shrinking to beyond 14nm, die pad pitch becomes smaller and bumps become finer dimensioned so that I/O pads can be laid out. In many cases, flip chip assembly is required because of layout considerations, performance, and cost effectiveness. Often, the fine pitch layout poses great challenges to existing bumping and flip chip assembly capability. This paper is to report an advanced redistribution layer (RDL) solution for a tighter pitch designed die so that that current flip chip assembly process can be used. The test vehicle die has two rows of staggered 40/80um pitch peripheral pads. The RDL is constructed with PBO-Cu-PBO stack and an advanced 10/10um L/S RDL design rule. After the RDL application, the bump pitch of the die is expanded into an area array flip chip type with 170um pitch. Mechanical, Electrical, Constructional analysis is reported in the paper. Assembly process and manufacturability with thermal compression flip chip technology is evaluated. Initial construction analysis and reliability test is conducted. The results clearly show that this RDL technology is feasible and potentially a viable choice for new Silicon node technology die with tight pitch. View full abstract»

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  • A high-speed test board design for 40GHz Bandwidth die

    Page(s): 60 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    It causes great challenge to the ordinary method to test the performance of the die when it comes to high frequency like 40GHz, especially for the optical die with some peripheral units, which causes extra difficulties with probes on the test bench. For the discontinuity of the impendence causes great loss for high-frequency signal, and it is difficult to place the die and the optical peripheral units on the test bench and to find a proper posture to conduct a precise experiment. A test board with a 3.5mm cable connector was designed to overcome these difficulties and to reduce the unnecessary loss caused in the test procedure. Dies connects to the test board via wire-bonding or flip chip. The trace/spacing changes from 70/30um to 880/560um. Considerable simulations were performed mainly for two purposes. Firstly, the model of 3.5mm connector and the connection with board was established in HFSS to search for the less discontinuities of the connector connecting to the board to reduce the loss in the process of the signal transmission. Secondly, the simulations of different trace design help to choose the route with less loss. Aside from the structure design, process and material and structure must be optimized to improve the performance of this package structure. View full abstract»

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  • A 3D package design with cavity substrate and stacked die

    Page(s): 64 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB) |  | HTML iconHTML  

    Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity-embedded substrate. Through hole via in the substrate provides the signal communication at a cost-effective way. This structure satisfies the high standards for mobile products packaging by reducing the package size and cost and maintaining functionality. In this paper, some details on the design concepts of the structure are introduced. Then, since the geometric configuration of the bonding wire is unusual, the electrical performance of the wire bonds of the structure is predicted by HFSS. Though the wire bond is long, simulation results shows that it is still suitable for the speed circuits below 3GHz. On the other hand, the two-step cavity effectively improves the isolation capability between different die. Moreover, the fabrication process of this structure is presented in detail to access the design. Finally, the functional test of the end products is performed and the end products work well. View full abstract»

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  • Modeling and simulation of Cu TSV electroplating for wafer-level MEMS vacuum packaging

    Page(s): 68 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (963 KB) |  | HTML iconHTML  

    3D integration and packaging with through silicon via (TSV) is a promising method to overcome the limitation of integration scale in Micro-Electro-Mechanical Systems (MEMS) packaging. It is helpful to realize high density and reliability micro-devices. The technology of fabricating copper (Cu) TSVs by electroplating is applied to provide signal connection in vertical direction. However, the fabrication of defect-free and economical TSV is our destination. In this paper, the Cu deposition mechanism was analyzed and the process was expressed by a series of electrochemical equations. Finite element models (FEM) were built to simulate the double-sides Cu electroplating processes in wafer-level TSVs. Part of the 370μm thick and 100mm diameter double-sides polished silicon wafer model was built in the simulation. Simulation results show that defect-free Cu TSVs were achieved using optimized double-sided electroplating methods. Additives added in electrolyte affected the Cu deposition velocity and direction to a certain extent. Comparing to other common electroplating methods, double-sided electroplating was economy. Finally, Cu TSVs were successfully fabricated and applied to the vacuum packaging of MEMS. View full abstract»

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  • Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

    Page(s): 73 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB) |  | HTML iconHTML  

    Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new reliability challenges. This paper presents the latest progress in TSV non-destructive stress testing by means of micro-Raman microscopy, a technique which is approved to be the method of choice for identifying stress on silicon surface. The principle of micro-Raman microscopy for TSV measurement is illustrated. By using commercially available micro-Raman microscopy tools, silicon stress around vias having a diameter of 30 μm and a depth of 160 μm has been visualized under optimized conditions. View full abstract»

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  • A new type of wafer level package based on silicon substrate

    Page(s): 76 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB) |  | HTML iconHTML  

    WLCSP (wafer level chip scale package) has been well accepted within modern industry which brings not only the reduction of package size, but also good thermal performance vs. more traditional peripherally leaded packages. At the mean time, WLCSP feathers can significantly lower manufacturing costs. One of the barriers for WLCSP package to be accepted in the industry is the lack of existing and mature SMT and PCB technology with more and more tightened pitches of solder balls. Therefore, demands for cost-efficient packages come out when ball pitch is tightened less than 0.4mm. A new package way named Si-BGA is introduced in this paper. This package related process such as RDL and bumping, chip to wafer, flip-chip bonding, and capillary underfill is introduced. The structure of the prototype is characterized and the die level reliability is tested. The Si-BGA package demonstrated good reliability and can be used in low-k products. View full abstract»

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  • A kind of 3D hybrid assembly structure and technology

    Page(s): 79 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    In order to achieve more functions in certain size of the chip, and avoid RC delay caused by long-range interconnect under high density 2D encapsulation at the same time, the researchers focused on the Z direction - 3D packaging. With the increase of storage capacity, and the large scale of data logic fever problems will more and more obvious. So it will not be able to an unlimited number of laminated chips. Many established corporations in the world has developed 3D package. This paper introduces a kind of 3D hybrid assembly structure and technology. 3D hybrid assembly technology can realized a high level of integration and systematization, and the requirement for the thickness of chips is not high. Besides the five substrates are respectively bonded with the five metal surface of the metal shell, it is advantageous to the heat conduction and dissipation. It improves the heat dissipation problems, so it's better to the common stack type 3D encapsulation. View full abstract»

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  • Cu-Sn low-temperature stack bonding for 3D packaging

    Page(s): 84 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (566 KB) |  | HTML iconHTML  

    In this paper, a three-dimensional (3D) chip bonding technology using Cu-Sn solder was described. First of all, the interdiffusion process of elemental Cu and Sn in the bonding region was discussed, and some key factors were identified to influence the performances of bonding layer: temperature, pressure, atmosphere and annealing time. Scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the bonding layer in solder joints before and after annealing. Then, bonding experiments were carried out to determine the optimal parameters of the Cu-Sn bonding, and 3D stacking bonding with TSV (Through Silicon Via) and Cu-Sn microbunmps was finished. Finally, the strength of bonded layers was characterized by shear testing and tensile testing, and the electrical and thermal properties of bonded layers were tested. All the results have been compared with that of Cu-Cu thermal compression bonding. View full abstract»

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