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2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

20-23 Jan. 2014

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  • [Front cover]

    Publication Year: 2014, Page(s): 1
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  • 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) [Copyright notice]

    Publication Year: 2014, Page(s): 1
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  • Table of contents

    Publication Year: 2014, Page(s):1 - 6
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  • Call for designs: University LSI Design Contest ASP-DAC 2015

    Publication Year: 2014, Page(s): 1
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  • Call for papers - ASP-DAC 2015

    Publication Year: 2014, Page(s): 1
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  • Welcome to ASP-DAC 2014

    Publication Year: 2014, Page(s):1 - 2
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  • Message from technical program committee

    Publication Year: 2014, Page(s): 1
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  • University LSI design contest

    Publication Year: 2014, Page(s): 1
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  • “All Programmable SOC FPGA for networking and computing in big data infrastructure”

    Publication Year: 2014, Page(s):1 - 3
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  • Best Paper Award

    Publication Year: 2014, Page(s): 1
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  • University LSI Design Contest Awards [2 awards]

    Publication Year: 2014, Page(s): 1
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  • 10-Year retrospective most influential paper award

    Publication Year: 2014, Page(s): 1
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  • Organizing committee

    Publication Year: 2014, Page(s): 1
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  • Steering committee

    Publication Year: 2014, Page(s): 1
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  • Technical program committee

    Publication Year: 2014, Page(s):1 - 3
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  • University LSI design contest committee

    Publication Year: 2014, Page(s): 1
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  • List of reviewers

    Publication Year: 2014, Page(s):1 - 2
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  • Author index

    Publication Year: 2014, Page(s):1 - 18
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  • Normally-off computing project: Challenges and opportunities

    Publication Year: 2014, Page(s):1 - 5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    Normally-Off is a way of computing which aggressively powers off components of computer systems when they need not to operate. Simple power gating cannot fully take the chances of power reduction because volatile memories lose data when power is turned off. Recently, new non-volatile memories (NVMs) have appeared. High attention has been paid to normally-off computing using these NVMs. In this pap... View full abstract»

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  • Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"

    Publication Year: 2014, Page(s):6 - 11
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB) | HTML iconHTML

    This paper presents novel processor architecture for HP-processor with nonvolatile/volatile hybrid cache memory. By simulations of high-performance (HP)-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM can be reduced by over 90 % with little degradation of processor performance. The presented architecture with nonvolatile memory hier... View full abstract»

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  • Normally-off MCU architecture for low-power sensor node

    Publication Year: 2014, Page(s):12 - 16
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    Sensor nodes are used extensively in order to gather real-time information in the social environment and natural environment. And the production volume of sensor nodes is much increased with the development of cyber-physical systems. Therefore, it becomes important how to reduce the power consumption of huge sensor nodes. In this work, normally-off architecture of microcontroller for future low-po... View full abstract»

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  • Normally-off technologies for healthcare appliance

    Publication Year: 2014, Page(s):17 - 20
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (699 KB) | HTML iconHTML

    Battery mass and power consumption of wearable system must be reduced because the key factors affecting wearable system usability are miniaturization and weight reduction. This report describes a wearable biosignal monitoring system using normally-off technologies to minimize the power consumption. Especially we focused on daily-life monitoring and electrocardiograph (ECG) processor. Our system em... View full abstract»

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  • A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

    Publication Year: 2014, Page(s):21 - 22
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2 resulting in the... View full abstract»

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  • A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor

    Publication Year: 2014, Page(s):23 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950μW at 5.5 GHz. View full abstract»

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  • A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits

    Publication Year: 2014, Page(s):25 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (525 KB) | HTML iconHTML

    A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process w... View full abstract»

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