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Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th

Date 11-13 Dec. 2013

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Displaying Results 1 - 25 of 180
  • [Front matter]

    Page(s): 1 - 49
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    Freely Available from IEEE
  • 2L OMEDFC development for larger package to die size ratio in thinner core

    Page(s): 1 - 4
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    The development of a thinner core (:100um) laminate array based exposed die fcCSP package with package to die area ratio > 12, package total height maximum 0.77mm that meets the JEDEC <; ±100um warpage requirement is discussed. The same approach used for the 150um thick core exposed die fcCSP technology was used for this work, namely finite element modeling to guide the choice of mold compound types and properties, mold chase design, substrate core material & core thickness. The development of the 2-Layer Over-Molded Exposed Die Flip Chip device (2LOMEDFC) involved down selecting from a variety of potential candidate materials and doing some initial builds to verify the finite element molding results. After initial development and full characterization of the optimized substrate core material, core thickness, mold chase design and mold compound, a full qualification of assembled packages was completed. The qualification tests included MSL3 260C × 3 preconditioning followed by TC-B 1000cycles, uHAST 96hrs and bHAST 264hrs. To insure there were no delta function reliability effects, some of the qualification tests were extended beyond JEDEC standard times, TC-B 2000cycles, uHAST 192hrs. View full abstract»

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  • Wire sweep characterization of multi-tier palladium-copper (Pd-Cu) wire bonding on LQFP package using low alpha green mold compound

    Page(s): 5 - 10
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    Controlling wire sweep is critical in transfer molding process as excessive results in shorting of wires, which in turn cause electrical failure. Therefore, understanding the effects of various factors on wire sweep is crucial to ensure processability and high yield for Pd-Cu wire production. In this study, wire sweep characterization carried out on Low Quad Flat Package (LQFP) package subject to various wire location, mold flow direction, wire length, wire pitch and wire angle. Fractional factorial design of experiment (DOE) is performed using 4 factors and 3 center points to identify key molding parameters which influence wire sweep. Wire sweep performance is also investigated under various mold cavity temperature, die thickness and wire loop height. Wire location is found to be the most significant factor that affects wire sweep percentage. A positive correlation is found for the wire length and wire sweep percentage. The prediction profiles show that longer transfer time improves wire sweep performance. Optimum mold parameters are identified using JMP statistical analysis software in order to improve the wire sweep performance. It is also noteworthy that a thicker 11 mils die gives better wire sweep performance compared to a 7 mils die. A mold cavity temperature of 175°C gives lower wire sweep percentage compared to 165 °C and 185°C. In conclusion, the wire located at segment F of corner 4 (mold gate at corner 1) experiences the worst wire sweep due to longer wire length and mold compound turning effect. Optimum compound fluidity, lower wire loop height and optimized molding parameters are determined to be the essential factors that improve wire sweep performance during mold encapsulation process. View full abstract»

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  • CVQFN package development

    Page(s): 11 - 14
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    DR-QFN / MR-QFN, is a conventional leadframe based QFN package in Dual-row / Multi-Row design, which provides QFN package configuration with higher IO up to ~100 counts. At present, TI (Texas Instrument) has been providing polyimide tape type substrate with Ball Grid Array package named as MicroStar Junior BGA™(u*JrBGA™) for 100 more IO counts requisition. By applying the concept of Cu trace routing in polyimide tape substrate of u*JrBGA™™ instead of the ordinary QFN leadframe and then filling with solder resist (SR), an advanced multi-row QFN package is then reborn to support for more IO pin counts in QFN configuration. And package total thickness could be thinning down to 0.4mm. This advanced multi-row QFN package is named as Cu via QFN (CVQFN). Apart from the standard etching process for leadframe (Cu trace) routing, the leadframe (Copper Trace) for CVQFN adopts the plating process. Solder resist filling process is another employed process to sustain the 75 um thin leadframe (Cu trace) for the rest assembly process. Affirmatively, the goal is achieved to compete with current Dual-row / Multi-Row QFN (DRQFN/MRQFN) by offering the same thermal dissipation, package outline and foot print pattern. It also provides ultra thin package solution. Package reliability, Assembly manufacturability, and SMT BLR are discussed in this report. This report also describes this CVQFN can get rid of the mold flash issue existed in conventional MR-QFN/DR-QFN. View full abstract»

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  • Thermosonic ball bonding behavior of Ag-Au-Pd alloy wire

    Page(s): 15 - 20
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    Thermosonic wire bonding is a well-known process which combines heat, ultrasonic energy and force to bond small wires to complete an electrical path from a metalized surface on a microchip to another metalized surface on the substrate of the circuit and the bonding occurs through the process of atomic diffusion. The bonding wire materials presently used in the industries are primarily gold (Au) and recently the use of low cost copper (Cu) and palladium coated wire (PdCu) have increased significantly. However, due to the increasing price of Au and reliability concerns with the Cu and PdCu wire has led to the search of alternative bonding wire materials in which silver (Ag) or silver alloy wire (Ag alloy) has emerged as the preferred choice. Cu and PdCu wire induces a higher stress on the bond pad and underlying structure due to its inherent hardness value. Ag has similar mechanical properties as Au while it's cheaper and has higher thermal and electrical conductivity as compared to Au. When compared to Cu, Ag is similar in conductivity, but softer in terms of mechanical properties. The pure Ag bonding wire has some issues such as unstable free air ball (FAB) shape and poor reliability. To overcome these issues, alloyed Ag wire (Ag-Au-Pd) was developed and their FAB formation, bondability and reliability were studied. The package used is BGA type and the pad composition is Al-1%Si-0.5%Cu. Ag alloy wire delivers good and stable bonding capability using nitrogen as ambient gas. Both the bonded ball and stich bonding show good bond integrity. The reliability is determined by the high temperature storage life test (HTSL) test. Intermetallic compound (IMC) growth behavior during reliability test is characterized by the scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Two types of IMCs Ag2Al and Ag3Al were observed. No failure or voids are observed in the bulk IMC or metal-IMC interface after the HTSL test at 150C for 1000 h- s. Additionally these IMCs are fabricated in bulk and their resistivity and co-efficient of thermal expansion (CTE) properties are characterized to understand the likely source of failure of the Ag-Al bond. The CTE of the Ag3Al is lower than the Ag2Alwhich could be attributed to the lower stretching of lattice constant of former at higher temperature. The interface between the Al and Ag2Al is likely source of crack generation and failure because of the high CTE difference between them. The resistivity of the Ag3Al phase was found to slightly higher than Ag2Al. The information regarding the properties of Ag-Al IMCs are important for the finite element and quantum mechanics based first principle calculation and to ultimately predict their behavior in real life situation. The Ag alloy wire show floor life time of minimum 10 weeks based on bonded ball shape, workability and bondability test and there is no visible appreciable degradation of pull strength and bonded ball shape overtime. Ag alloy wire bonding has the potential to become an emerging technology as an option in microelectronic packaging. View full abstract»

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  • Effects of metallic nanoparticle doped flux on interfacial intermetallic compounds between Sn-3.0Ag-0.5Cu and copper substrate

    Page(s): 21 - 26
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    Intermetallic compounds (IMCs) formed between solder and substrate play a vital role in determining the long term reliability of microelectronic packages. Various attempts have been made by the researchers to control the morphology and thickness of IMC layers. The aim of this study is to investigate the effects of nanoparticle dopants into flux on the morphology and thickness of interfacial intermetallic compounds layers. Different types of nano-sized metallic particles were studied to understand their effects on the wetting characteristics and interfacial microstructural evaluations after first reflow by adding nanoparticles to flux at various percentages. Nanoparticles were dispersed manually with a water soluble flux to prepare a nanoparticles doped flux which was placed on the copper substrate. Lead-free Sn-3.0Ag-0.5Cu (SAC 305) solder balls of diameter 0.45mm were then placed on top of the flux and were reflowed in a reflow oven at a peak temperature of 240°C for 45s. Wetting area, contact angle and interfacial microstructure were investigated by optical microscopy, scanning electron microscopy (SEM), field emission scanning electron microscopy (FESEM) and energy-dispersive x-ray spectroscopy (EDX). It was found that doping of cobalt (Co) and nickel (Ni) nanoparticles with flux was successful in incorporating Co and Ni into the solder joint. Microstructural observations showed that both Co and Ni nanoparticles changed the interfacial morphology from a scallop to a planer type. This was suggested to be caused by alloying effect of these elements. In case of Co, this morphological change was evident down to 0.25 wt% Co addition to flux. For Ni, this effect was notable even at 0.1 wt% Ni addition to flux. Therefore, Nano doping of flux can be successfully used to cause in situ targeted alloying at the solder/substrate interface. View full abstract»

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  • Photo-dielectric polymers material characterizations for 3D packaging applications

    Page(s): 27 - 32
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    When considering wafer level packaging (WLP) applications, the use of dielectric polymer materials becomes more relevant for reliability performance. Indeed, polymer materials can have excellent dielectric performances with a processability at lower thermal balance. Their mechanical properties also offer a better compliance between the silicon 3D stack and the organic substrate underneath, improving the overall Front-End / Back End compatibility. This study reports the thermo-mechanical behavior and properties evaluation of the most advanced photo-sensitive dielectric polymers with higher resolution available in the market. It will allow direct comparisons between different dielectric polymer materials with the focus of stress control and thermal stability. First part of the paper will present thermal and mechanical characterization of these polymers performed with the same experimental conditions. Second part will present the advantages and limitations of each measurement characterization technique. And finally, the most relevant characterizations will be extracted in order to compare such dielectric polymers for 3D packaging applications. View full abstract»

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  • A novel manufacturing technology for tensile test specimens for the characterization of copper in plated through holes (PTH)

    Page(s): 33 - 36
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    Plated Through Holes (PTH) in Printed Circuit Boards (PCB) are exposed to high thermal loads during the manufacturing process and in field application. This is due to a significant difference in the coefficients of thermal expansion between base material (epoxy resin) and copper barrel. For the assessment of the PTH reliability, the knowledge of the material properties of the electro-deposited copper is of great importance. In this article the elongated hole specimen technique is introduced as a novel manufacturing technology for tensile test samples. With this simple and inexpensive method, stress-strain curves of copper layers are generated for the first time, with specimens that have similar deposition conditions and roughness as the copper barrel within the PTH. The method can be integrated into the PCB series production without additional cost of material or expenses and is particularly suitable for in-line process control of electroplating. With the film-like sample tensile tests were carried out successfully in an ambient temperature range of 20°C to 140°C. The material data is compared with tensile specimens deposited on the surface of a FR4 substrate. View full abstract»

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  • Applications of XPS and TOF-SIMS in the investigation of PCB package delamination

    Page(s): 37 - 39
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    In this study, die to printed circuit board (PCB) interfacial failure was investigated. Instead of using conventional Scanning Electron Microscope - Energy Dispersive X-ray Spectroscopy (SEM-EDX) and Fourier Transform Infrared Spectroscopy (FTIR) for bulk material analysis, advanced surface analysis techniques such as X-ray Photoelectron Spectroscopy (XPS) and Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) were employed to analyze the delamination between die and PCB. High percentage of siloxane bond was revealed at the failure interface using XPS. TOF-SIMS was used to further validate that the siloxane bond belongs to Polydimethylsiloxane (PDMS) from blue tape. Combining both XPS and TOF-SIMS analysis techniques, it was shown that the die to PCB delamination was attributed to PDMS contamination. View full abstract»

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  • A novel damage test evaluation of IC bond pad stack strength

    Page(s): 40 - 43
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    A novel damage test method is presented, to examine the mechanical strength or behavior of an Integrated Circuit (IC) bond pad stack. A micro-mechanical tester is employed for an indentation test where quasi-static load is applied on the IC bond pad. Any damage or cracking can be detected by the acoustic emission (AE) sensor system placed underneath the IC chip. This methodology provides an in-depth understanding of the damage mechanics and emergence in a complex structure as in the IC chip bond pad stack. As a consequence, weak designs or mechanically inferior layouts can be identified and avoided. View full abstract»

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  • Environmental ageing effects on the electrical resistance of silver-epoxy electrically conductive adhesive joints to a molybdenum electrode

    Page(s): 44 - 47
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    The electrically conductive adhesives (ECAs) provide a large amount of opportunities for the electronic manufacturing. They have much lower processing temperatures, so the heat impact on the electronic components can be reduced. It makes them suitable for interconnecting the temperature sensitive elements in the devices, for example in liquid-crystal displays or modules of flexible thin film solar cells. However, this type of interconnections has to overcome some challenges. As the contact to noble metals has relatively low electrical resistance and is stable to the environment loads, in the ECA joints to non-noble metals the degradation happens (increase of contact resistance, decrease of adhesion). That's why it is important to investigate such type of joints for stability under different ageing conditions. Most of the latest investigations in this field are concentrated on the ECA joints to Sn, because this non-noble metal is widely used in the electronic packaging. This system of contacted materials remains stable under the (120°C) thermal ageing, but suffer from increase of the contact resistance after heat/humidity ageing (85 °C/85% relative humidity) and accelerated thermal cycling (-40 to 125°C). Another contact of non-noble metal to ECA that needs to be investigated is Mo to ECA. Molybdenum is used as a back contact in thin film solar cell manufacturing and the ECAs are used for interconnection and assembling the individual cells in modules. The focus of this work is to investigate the contact behavior between ECAs and non-noble, molybdenum films under different ageing conditions. The experiments are focused on the electrical conductivity. The goal of the work is to investigate the degradation behavior of non-noble metal - ECA joints and to predict the reliability of this type of an electrical contact. View full abstract»

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  • Development of low-temperature drop shock resistant solder alloys for handheld devices

    Page(s): 48 - 52
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    As handheld devices become increasingly smaller and complex, there is a shift in reliability requirements of solder pastes. Considering that thermal management and drop resistance of such devices become more challenging, improved thermal fatigue and mechanical shock properties grow into must have requirements. Additionally, multi-step assembly process and a surge in use of temperature sensitive components bring additional challenges that necessitate the use of low temperature alloys. Here we present the findings of our Alloy Development Program on the next generation of low temperature alloys that can be used in reflow soldering temperatures from 170 to 200°C. By using micro-additives we have created low temperature alloys with superior mechanical properties, higher drop shock resistance and improved fatigue life. View full abstract»

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  • Developments in 2.5D: The role of silicon interposers

    Page(s): 53 - 55
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    Silicon interposers are a technology with a history of multiple incarnations over more than 20 years. Today, interposers with TSVs are considered an alternative to 3D IC structures where die are stacked on top of each other using TSVs. Applications for interposers with TSVs include ASICs for networking applications and FPGAs. Xilinx's Virtex-7 2000T FPGA was one of the first new products using a silicon interposer with TSVs for a partitioned IC design. Co-design with new packaging technology has resulted in a new FPGA that allows reduced system cost and increased performance with lower power. By not having to drive off-chip I/Os across PCB traces to adjacent FPGAs, high-performance applications that have previously used multiple FPGAs can be replaced with a single package solution that provides high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. The key to the performance gains is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer. Is this a unique application or are there other potential applications for interposers in applications with GPUs or ASICs? Today's interposers are passive structures, but there are potential for the use of integrated passives in the interposer. How do these applications differ from the technology introduced in previous generations? This presentation highlights the new drivers for the introduction of silicon interposers. The presentation also examines the latest developments in the infrastructure to support the development of this technology, including suppliers. The article also highlights the differences between adoption of today's interposers and the thin-film on silicon (MCM-D) of the past. View full abstract»

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  • Signal integrity study of high density through silicon via (TSV) technology

    Page(s): 56 - 61
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    This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions. View full abstract»

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  • An innovative and low cost Bi-layer method for temporary bonding

    Page(s): 62 - 66
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    The purpose of this work was to demonstrate the compatibility of Dow Corning's temporary bonding solution with EVG's 850XT universal temporary bonding and debonding platform. The proposed process made use of well-known processing steps and processing modules like spin coating. The process consisted of a release layer (Dow Corning® WL-3001 Bonding Release) and an adhesive layer (Dow Corning® WL-4050 or WL-4030 Bonding Adhesive) using an EVG® 850TB - 300 mm XT frame. Both layers of material were applied by spin coating on the device wafer side. In the frame of this study, silicon carriers were used. Bonding was performed under vacuum at room temperature. A post bonding bake step was applied using a hotplate. After subsequent backside processing steps, the room temperature debonding was performed. View full abstract»

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  • Simultaneous molding and under-filling for void free process to encapsulate fine pitch micro bump interconnections of chip-to-wafer (C2W) bonding in wafer level packaging

    Page(s): 67 - 72
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    The encapsulation of chips with fine pitch micro bump interconnections in chip-to-wafer (C2W) bonding has a known two steps process in wafer level packaging. First step is underfilling process that fills the gap between bumps underneath the chips. Under-filling process can either be using liquid dispensing which allow it to flow underneath the bumped chips by capillary force or using a non-flow under-fill material. The second step is molding process that encapsulates the entire C2W with a molding compound. Through simultaneous molding and under-filling process to encapsulate, the two steps will become a single step process. Although, this method has been widely used for flip-chip Ball Grid Array (BGA) packaging using Moldable Under-fill (MUF) material in transfer molding, it is not yet fully utilized for wafer level C2W packaging using MUF material in wafer level compression molding. One major challenge during under-filling is voids formation underneath the bumped chips as shown in Fig. 1. This study aims to implement simultaneous molding and under-filling to achieve a void free process in wafer level C2W packaging. Mold flow simulation using ANSYS FLUENT 14.5 commercial software is being used to predetermine the major factors affecting the voids formation. Based on the simulation result, we have identified several factors that can significantly affect the voids size. The identified factors are mold temperature, mold compound dispensing pattern and mold filling speed. The mold flow simulation results are being validated using test chips with 90um micro bump pitch in the actual molding experiment. We validated the actual void formation by comparing the result of low and high molding temperature, comparing round and straight line dispensing pattern and also validated the use of slower filling speed during molding process. The experimental result confirms the total elimination of voids formation during simultaneous molding and under-filling process. The experimental r- sult indicates that the actual molding perfectly match with the mold flow simulation result. View full abstract»

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  • Comparative investigation of double-layer and double-side micro-channel cooling for power electronics packaging

    Page(s): 73 - 77
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    In present work, micro-channel heat sink (MCHS) is integrated inside direct bond copper (DBC) for power electronics cooling. Based on commercial CFD code ANSYS Fluent, micro-channels are designed in back Cu-layer of DBC substrate with liquid water as coolant. Two advanced cooling structures, including double-layer (DL) and double-side (sandwich) micro-channel, are investigated. The sandwich structure with counter flows shows reduction in thermal resistance by 59%, 52% and 53% when compare with single-layer (SL), DL with unidirectional flows and DL with counter flows respectively. It also promises uniform temperature-distribution. View full abstract»

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  • Package-level thermal management of a 3D embedded wafer level package

    Page(s): 78 - 82
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    As the embedded wafer-level packaging (eWLP) technology evolves to capitalize on package-on-package (POP) technology, thermal analysis has been performed to investigate and improve the heat dissipation capability of the 3D package structure. 3D simulation models have been built to study the impact of the thermal properties (underfill material, passivation layer and mold compound) and geometries (over mold, passivation layer and Cu layer in RDL) on the package thermal performance. We also analyzed the thermal effect of the Cu percentage in each RDL layer. The top heat spreader, thermal via arry, bottom heat dissipation plate and two types of top thermal cases have employed to enhance the heat dissipation capability. In baseline conditions, without any enhancement structure, the 85°C temperature limit can be met, at a max total PoP power dissipation of 2W (Logic: 1.5W, memory: 0.5W). In the mobile device scenario, passive cooling solutions have been applied to the PoP structure, and a total power of 4W can be accommodated with the proposed cooling structures. View full abstract»

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  • Thermal management of hotspots using upstream laminar micro-jet impinging array

    Page(s): 83 - 87
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    The problem of heat removal is likely to become more severe due to the presence of hotspots in the integrated circuit chip. The heat dissipation capability of the upstream laminar micro-jet impinging array is investigated for hotspot cooling. Micro-jet impingement array cooling is an effective method of using liquids to cool electronics where high convective heat transfer rates are required. Several simulations have been implemented on the thermal structure of 4 tiny inline-aligned hotspots to evaluate the heat dissipation capability of the laminar micro-jet impinging array. The effects of the jet diameter, jet pitch and jet-to-wall distance on the Nusselt number, heat convection coefficient, Reynolds number and thermal resistance are studied. The limit of the dissipated heat fluxes of the considered thermal structure are evaluated for the hotspots of different sizes. View full abstract»

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  • What's inside my USB drive? — X-ray microscopy and X-ray nano CT for 3D packaging

    Page(s): 88 - 92
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    Electronics and microsystems technology are characterized by an ongoing miniaturization and a growing up of complexity of semiconductor components. These trends are described by Moore's Law and the terms “More Moore” and “More than Moore” . The most important driver of this development is the respective market of the final products driven by the costs. In this context the development of electronic and micro technical systems is inseparably connected with the corresponding electronics packaging and the required nondestructive testing methods. This paper presents fundamentals and applications for nondestructive evaluation of inner structures of electronics packaging for quality assurance and reliability investigations. The authors used two generations of conventional USB memory drives with stacked dies to present possibilities, evolution and limitations of high-resolution NDT methods for electronics packaging like X-ray diagnostics and Scanning Acoustic Microscopy. The focus is on the X-ray nano CT (computed tomography). As a highlight the paper describes the evaluation of wire bonding connections (gold wires) on a silicon die with copper metallization with X-ray nano CT. View full abstract»

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  • Chip Package Interaction(CPI) risk assessment on 28nm Back End of Line(BEOL) stack of a large I/O chip using compact 3D FEA modeling

    Page(s): 93 - 97
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    Chip Package Interaction (CPI) is a widely recognized quality and reliability challenge for flip-chip packages due to the ultra low-K materials used within the silicon Back End of Line (BEOL). This paper discusses a predictive finite element model developed to address this challenge. Furthermore, for advanced flip-chip package models, it is challenging to have the entire C4 bump array within the model due to the extremely large pin count (I/O) fitted at a fine pitch within a large die. As an example, for CPU chips, it is not uncommon to have chip contain over 10,000 C4 bumps. Accounting for such large bump count with FEA models, makes the analyses not just computationally expensive but also often impossible. The proposed study will try to address these challenges by demonstrating a “compact” 3D modeling approach for 28nm chip stack. The effective properties developed for C4 joints will also be adjusted to account for Cu pillar joints. Lastly, the model has been validated with full bump array models that do not use effective properties to confirm the usefulness and scalability of this approach. View full abstract»

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  • An advanced MEMS sensor packaging concept for use in harsh environments

    Page(s): 98 - 102
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    The presented package for harsh environment fulfills the demands to withstand high temperatures of 400°C, aggressive media and pressures up to 50 bar as it uses a steel membrane with an indenter which pushed on the center-boss structure of the sensor. Thus no transmitting media like oil is needed. The SOI sensor chip consists of a beam with an integrated center-boss which was realized using KOH structuring and DRIE (Deep Reactive Ion Etching/Bosch Process). The SOI technology has the distinct advantage that the piezo-resistors are not isolated by a pn junction from the dielectric substrate but by a buried oxide layer. In combination with a high temperature metallization, the SOI-chip is able to withstand the demands of high temperatures. The high temperature metallization consists of a sputtered Ti/TiWN layer that has been exposed to special RTA (rapid thermal annealing) process. Afterwards a TiWN and an Au layer are sputtered followed by an Au electro plating process. The chip has four piezoresistors that are arranged in pairs of longitudinal and transversal resistors which are compressed when pressure is applied. The four resistors are connected via conductors to a Wheatstone bridge. The sensor chip has a beam thickness of 25 μm and the center-boss has an area of lmm × lmm. The beam has a natural frequency of approx. 20 kHz. The sensor chip is mounted using Flip Chip technology to avoid a wire bond technology. It is mounted on a glass feed through on which stud bumps are located and conducted using thermo-compression process. The pressure range is set by varying the steel membrane thickness. This concept has a mayor advantage that the sensor chip can be used for various pressure ranges. The thickness of the steel membrane is chosen adopted to the pressure range, so that the deflection of the sensor beam is 12μm when the maximum pressure is applied. View full abstract»

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  • Technology for bipolar polycarbonate electrodes applied for intraoperative neuromonitoring

    Page(s): 103 - 107
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    The paper presents a novel bipolar electrode for continuous evaluation and identification of neural dysfunction. The hook-up design realized with a careful choice of biocompatible materials, enhances the easy of implantation and positioning of the electrode during the medical procedure. In this regard, the proposed electrode offers a promising alternative for applications in neural electrical stimulation and recording. View full abstract»

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  • Electrical functionalization of thermoplastic materials by cold active atmospheric plasma technology

    Page(s): 108 - 113
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    Plasmadust® is a new technology using cold active plasma for additive metallization of different substrate materials. For electronics production, in particular Molded Interconnect Devices (MID), thermoplastic materials can be structured with copper as power electronic conductive pattern. The main advantages of Plasmadust® are the controllable process temperature range between about 90°C and 180°C, the good adhesion of the metallization, the fast process speed of about 100 mm/s and the fast growing conductor tracks with about 15 microns thickness per cycle. Plate specimens were made of PA, a thermoplastic commonly used in automotive applications, with different process parameters. Conductor tracks applied onto the substrates consist of one line with different electrical and mechanical properties according to the process temperature and process speed. Additionally, the thickness and the width of the conductor track depend on the process parameters. The setting of the process speed turns out to be an important influence on the thickness and roughness of the conductor track that can be achieved on thermoplastic substrates. The investigated combination of thermoplastic and copper shows a constant bonding performance during thermal shock testing for 1000 cycles in the range of -40°C and +125°C. An exposure to humidity heat (85% r.h / 85°C) for 500 h has only marginal effects on the adhesion of the printed structures on the thermoplastic substrates, too. This highly promising results provide the base for further investigations to achieve a sufficient ampacity related to standard chemical PCB metallization processes. View full abstract»

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  • Study of power integrity challenges in high-speed I/O design using power rails merging scheme

    Page(s): 114 - 117
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a greater challenge to the design of a power distribution network (PDN). Power rails merging is a popular option adopted today in a PDN design as the provision of numerous power rails is no longer feasible due to form factor limitation and cost constraint. In this paper, a study of power integrity challenges in a high-speed input/output design using power rails merging scheme is presented. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important. View full abstract»

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