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Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Research in

Date 19-21 Dec. 2013

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Displaying Results 1 - 25 of 60
  • [Front matter]

    Page(s): 1
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  • [Copyright notice]

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  • Message from the organizing committee

    Page(s): 1 - 7
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  • Tutorial program schedule

    Page(s): 1 - 12
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  • A low power continuous time band pass sigma delta modulator using linearity enhanced OTA

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (871 KB) |  | HTML iconHTML  

    This paper presents a low power continuous-time bandpass sigma delta modulator for analog to digital converter (ADC) over 5 MHz band. The modulator consists of a fourth order design operating at a Sampling Frequency of 280MHz. The operational transconductance amplifier (OTA) is linearized by using source degeneration technique. This paper investigates the effect of OTA linearization on the modulator performance. It is observed that Signal to Quantization Noise Ratio (SQNR) with a non-linear OTA is of 46.6dB and it is 55.07dB with a Source degenerated OTA showing a marked increase of 1.5 bits(9 dB) in resolution of modulator. Further, optimum transistor sizing leads to a very low power consumption of 10.9mW and a figure of merit of 2.445pJ/bit. View full abstract»

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  • Cascaded load inverter configuration for induction cooking application

    Page(s): 7 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1326 KB) |  | HTML iconHTML  

    In this paper a single full bridge resonant inverter with independent output power control of two cascaded loads for induction cooking application is presented. In proposed configuration, the full bridge inverter can be operated with constant switching frequency and constant duty ratio for efficient zero voltage switching. Independent output power control of each load is done by varying the duty ratio of respective switching device at load. The proposed configuration can be extended to multiple loads. It is more reliable for multiple load induction cooking application. For theoretical predictions, the proposed configuration of cascaded load inverter configuration for induction cooking application with independent control of each load is simulated in ORCAD (P-Spice) environment. View full abstract»

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  • A new approach to fast tracking and low cost single exponential model photovoltaic system

    Page(s): 13 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    The work portrayed in this paper furnishes knowledge about advanced solar photovoltaic (PV) conversion system. This PV system is fast and tracks more output power than conventional PV systems. In literature, the PV parameters of a double exponential model were designed with the help of Levenberg-Marquardt algorithm. In this paper, the PV parametric values were taken into consideration and implemented in a single exponential model with curve fitting method. The results of a conventional PV system and it was observed are compared with the implemented PV system and observed that, the implemented PV system tracks 23 % excess power than the conventional one. Finally, the PV system is implemented with a series of 2000 interconnected PV cells for higher voltage applications, due to its unfussiness and lower cost. The MATLAB simulated models are presented and discussed. View full abstract»

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  • Modeling of redundancy analyzer in BISR for RAM

    Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (658 KB) |  | HTML iconHTML  

    In the current SoC implementation embedded memories are most widely used cores. They usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Embedded memories have become very vulnerable to even minor process variations, resulting in low manufacturing yield & reliability. Efficient yield-enhancement techniques for embedded memories are thus important for SoC. The Built in Self Repair (BISR) includes two modules Built in Self Test (BIST) and Built-In Redundancy Analysis (BIRA). The BIRA circuit performs the redundancy allocation using the proposed RA algorithm. The purpose of RA is to allocate appropriate redundant (spare) memory elements to replace the defective cells, such that the utilization of the spare elements can be optimized. In a memory with BISR, the RA collects the fault information from the BIST. RA performs the analysis after the fault bit-map of a defective memory is constructed. In this paper, it is proposed to model a RA technique for a 2D Random Access Memory of 512 bit with spare rows and columns. This Analyzer decides which spare element to be allocated for a fault adaptively by considering the fault count on each row/column. The model is simulated using Aldec Active HDL version 6.3 and synthesised using Xilinx ISE tool 9.1. View full abstract»

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  • A 4.2GS/s 4-bit ADC in 45nm CMOS technology

    Page(s): 24 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    In this paper an analog to digital converter architecture is introduced. The proposed design is based on a mixed approach of flash type ADC and SAR type ADC. This design offers lesser number of comparators and so low power consumption with much less circuit complexity in comparison to conventional flash ADC architecture. Based on the proposed idea, a 4-bit ADC is simulated in Cadence virtuoso Tool using 45nm CMOS technology with power supply voltage of ± 0.6 V. Maximum sampling speed of ADC is achieved as 4.2 GS/s. The ADC consumes 72μW of power. The measured INL and DNL are 0.40 LSB and 0.42 LSB respectively. View full abstract»

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  • Implementation of a full adder circuit with new full swing EX-OR/EX-NOR gate

    Page(s): 29 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (541 KB) |  | HTML iconHTML  

    The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying the existed circuits. Full adder is an essential component for the design and development of all type of processors like digital signal processors, microprocessors etc. So, in this paper a full adder is constructed by using the new proposed Ex-OR/Ex-NOR gate. All the existed and proposed circuits have been simulated using Cadence 180nm CMOS technology file at different supply voltages ranging from 0.6 V to 3.3 V. The simulation result demonstrates that the delay, power dissipation and power-delay product (PDP) of the proposed design are better than existed design. View full abstract»

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  • A power gating GALS interface implementation

    Page(s): 34 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (749 KB) |  | HTML iconHTML  

    In today's nanometric VLSI designs achieving both power and performance targets is the top most priority for design closure. Globally asynchronous locally synchronous (GALS) architectures can offer less dynamic power and improved performance due to absence of global clock. In GALS SoC architectures each synchronous blocks runs on their local clocks. Synchronous blocks communicate with each other by pausing their local clocks using an asynchronous interface which is implemented using various handshake protocols. However any synchronous block which has to wait long time for data from another block need to be in idle state and as a result will dissipate significant leakage power in nanometric designs. Power gating is an effective technique to reduce leakage power of an idle circuit in synchronous designs. However implementing such power gating interface in GALS architecture is a challenge in the absence of clock. Thus to reduce the leakage power in ideal blocks which are waiting for the data, a new GALS wrapper interface was proposed which can generate power gating sequence. To corroborate the proposed interface a GALS 8051 was implemented using Synopsys SAED 90 nm libraries. The power gating sequence of 8051 asynchronous wrappers are used to gate the power of Random Access Memory (RAM) block while Arithmetic Logic Unit (ALU) block is busy in doing arithmetic operations. The experimental results show a 30% reduction in leakage power of RAM block due to power gating. View full abstract»

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  • A high gain, high CMRR two-stage fully differential amplifier using gm/Id technique for bio-medical applications

    Page(s): 40 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    This paper presents a well-defined method for the design of a high gain, high CMRR two-stage CMOS operational amplifier using 0.18μm CMOS technology for Bio-medical applications. The Op-amp consists of a cascade of Folded-cascode differential amplifier in first stage followed by a fully differential amplifier with PMOS current source load in second stage. The gm/Id technique is employed in designing the Op-amp. Trade-offs among the factors such as bandwidth, gain, phase margin, bias currents, signal swing, slew rate and power dissipation are explained. Common mode feedback is employed in the design for high CMRR. The designed Op-amp has a gain of 106.31dB, CMRR of 131.02dB, phase margin of 57.53°, power consumption of 685μW and a Slew rate of 3.87 V/μs for a 3.3V power supply in the design corner TT. As the number of stages increase, stability of op-amp is a concern. So, Frequency compensation techniques are employed for the proposed design. This design provides a considerable insight into the overall operation and advantages of CMFB network. This design obtains a high gain and high CMRR which makes it suitable for Biomedical applications. View full abstract»

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  • 2:1 Multiplexer based design for ternary logic circuits

    Page(s): 46 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    This paper presents a design methodology using multiplexers to implement any ternary logic function with carbon nanotube field effect transistors (CNFETs). Ternary logic is one of the promising alternatives to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects and chip area. The paper presents a design methodology which uses the combination of Binary 2:1 multiplexers and Ternary multiplexers, to implement Ternary logic circuits. A 1-bit half adder circuits is implemented using the proposed methodology. The proposed implementations are compared with the existing designs for parameters like delay, power etc. Two kinds of 1-bit half adders i.e., delay optimized and power optimized half adders have been designed. Simulation results indicate that the proposed multiplexer based 1-bit half adder design results in 58% average power reduction and 64% power delay product reduction when compared to the existing multiplexer based design. View full abstract»

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  • Modeling and simulation of static var compensator to enhance the power system security

    Page(s): 52 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    Today's Power system is more complex and consequently it would lead to less security. To meet the demand and better security levels with existing transmission lines, the Flexible AC Transmission System (FACTS) devices are one of the alternates. In this paper a Newton Raphson(NR) algorithm was developed to find out the best operating point of a Static Var Compensator(SVC) for the enhancement of system security. The proposed algorithm minimizes the security index iteratively. Security index indicates the overload level of transmission lines. The proposed algorithm is verified by IEEE 5 bus system. Line power flows and bus voltages and bus angles are obtained by the Newton Raphson algorithm and the security index is calculated for both the cases with and without SVC. The results show that the voltage profile can be enhanced and the security margin increased by applying the proposed algorithm. View full abstract»

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  • High voltage LDMOSFET modeling using BSIM6 as intrinsic-MOS model

    Page(s): 56 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    Here, we report high voltage MOSFET modeling using BSIM6 model. The model has two components - intrinsic MOSFET channel of LDMOS modeled by BSIM6 and a drift region modeled by non-linear drift resistance. BSIM6 is the next generation bulk MOSFET model in BSIM family of models. It also have the model of Self Heating Effect (SHE) which is very important for high power devices like LDMOS. This model shows good behaviour over wide range of gate and drain bias conditions including convergence. Some of the effects like Quasi-saturation, self-heating and impact ionization are modelled by the combination of BSIM6 and drift-resistance models. We have validated this model on the simulated characteristics generated by TCAD and then, on the measured characteristics of a LDMOS device, where it shows excellent accuracy over entire bias range. View full abstract»

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  • Simulation & analysis of different parameters of various levels of cascaded H bridge multilevel inverter

    Page(s): 62 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (937 KB) |  | HTML iconHTML  

    Cascaded multilevel inverters synthesize a medium-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltages and input currents and also outstanding availability due to their intrinsic component redundancy. Due to these features, the cascaded multilevel inverter has been recognized as an important alternative in the medium-voltage inverter market. This paper presents output voltage waveforms and total harmonic distortion (THD) for single phase and three phase cascaded multilevel inverter starting from 5-level to 15-level. Simulation results show that as the number of levels increases the % THD will be reduced. View full abstract»

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  • BCI controller based on imagery activity using shortest path algorithm

    Page(s): 68 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    Assistive robotics will help the physically disabled persons in many ways. They attempt to restore human abilities that have been reduced or lost by disease, accident, or old age. In this paper we described about how the P300 based Brain Computer Interface (BCI) system controller will work and employed to improve the conventional controlling methods by interpreting the normal BCI system with path planning technique like Dijkstra's algorithm for an autonomous robot. P300 data collected from a healthy subject based on specified imagery brain activity is applied as the input to the proposed controller by adopting those robot features to the wheel chair by using National instruments LabVIEW and its hardware. View full abstract»

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  • Power efficient reconfigurable charge pump for micro scale energy harvesting

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    One of the key challenges in micro scale energy harvesting system is that the output voltages produced by the tiny transducers are very low (0-0.4V). Therefore a charge pump(CP) with high voltage step up ratio is essential to boost the voltage, and charge an energy buffer for storage. Conventional Linear and Fibonacci charge pumps have better current driving capabilities at higher and lower voltage ranges respectively. This paper presents a reconfigurable charge pump topology which utilizes merits of both Linear and Fibonacci charge pumps for micro scale energy harvesting applications with wider range of input voltages. Through this approach we are extending lowest operating voltage by 50mv as compared to a standalone linear charge pump. The proposed charge pump has been designed with UMC 180nm technology and the circuit simulations demonstrate a wider range of input voltages as compared to conventional charge pumps. Through this we are able to extend lower input voltage limit from a value of 230 mV to 180 mV. View full abstract»

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  • Robust, ultra fast data sensing technique for low power asymmetrical SRAM with self-shut-off feature

    Page(s): 77 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1535 KB) |  | HTML iconHTML  

    Single ended data sensing for asymmetrical low voltage memories has become a topic of much interest due to its application in very low energy computing and communication. In this paper, we present an ultra-high-speed (UHS) data sensing scheme for single ended near threshold asymmetric static random access memory (SRAM) design in a 45nm standard CMOS process. The proposed bit-line decoupled single ended sense amplifier (BD-SESA) deactivate a low-Vth latch by fixing the gate of NMOS device to ground (gnd) which makes the proposed scheme vulnerable to wrong latching for bitline offset due to process variation. We rigorously investigated the impact of process, voltage and temperature (PVT) variation on sensing delay, standby leakage and sensing failure and achieved commendable improvement in power dissipation and sensing delay. A self shut-off mechanism (SSM) significantly reduces voltage swing at read bit-line (RDBL) which further results in reduced power dissipation. Extensive post-layout simulation has verified that our design is insensitive to bit-line capacitance and achieves sensing delay of 297.7pS and 411.7pS at 1V and 0.8V supply respectively and offers 52.56% and 60.36% better mean with 61. 3% and 19.7% less silicon area than designs in comparison. View full abstract»

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  • Analysis of induction generators and advanced power electronic converters for wind energy conversion technology

    Page(s): 83 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1086 KB) |  | HTML iconHTML  

    The advancements in power electronics technology has made the usage of wind energy conversion technology (WECT) dominant in electrical power generation compare to other technologies. In this paper, modeling, and analysis is made for latest power electronic converter topologies and Induction generator topologies (IG) used in WECT. The mathematical models are built in MATLAB environment. The dominantly used IG i.e., self excited induction generator (SEIG) and Doubly-fed induction generator (DFIG), Wind modeling, Turbine Modeling, Gear shaft modeling are discussed in detail. This paper concludes by evolving new methods for stabilization of wind farms with new power converter topologies from the obtained results. View full abstract»

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  • Modeling and simulation of 8/6 pole switched reluctance motor with closed loop speed control

    Page(s): 89 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB) |  | HTML iconHTML  

    A switched reluctance (SR) motor has a doubly salient pole structure. A stator has concentrated windings on each pole, while a rotor is only made of iron core. Therefore, the SR motor is expected as a low cost, extremely robust, variable speed motor. The performance of the SR motor greatly depends on magnetic properties of core material since it consists of only laminated-core and windings. However, some of its disadvantages are noise, torque ripple and low torque per unit volume. In this paper mathematical modeling of switched reluctance motor is carried out various equations of SRM are clearly described. In this paper we have developed simple SRM model without nonlinearities and saturation effects. The proposed model is operated in open loop and further it is operated in closed loop. PI controller is employed for closed loop operation. Finally MA TLAB/Simulink based model is developed and simulation results are presented. View full abstract»

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  • An efficient shielding effectiveness analysis of rectangular box perforated with numerous apertures by transmission line model

    Page(s): 96 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (337 KB) |  | HTML iconHTML  

    The shielding effectiveness of a metallic shield perforated with numerous apertures of various shapes is evaluated in this paper. Here an appropriate admittance which takes the mutual coupling between the apertures into account is considered to represent the array of apertures. This method is applicable to an array of square, circular and rectangular holes of rectangle and square configurations. Results from the simulations demonstrate that: more coupling energy is obtained when the frequency is below the frequency of resonance and shielding and enclosure are closer; when the resonance is in between the aperture and enclosure, it causes in the metal shield a reduced shielding effectiveness; lower frequencies display better shielding than higher frequencies; the effectiveness of shielding of a single hole is worse than of a multi-hole for identical areas. This method is extremely efficient and easy to implement compared to numerical techniques. View full abstract»

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  • Impact of channel length & oxide thickness variation in an asymmetric SGOI-TFET

    Page(s): 103 - 106
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    In this paper we have optimized a asymmetric SGOI based TFET for low power applications with VDD = 0.5 V. Here, we have observed the variation of channel length and oxide thickness on the device which affects switching figure of merit such as subthreshold swing, Ion and Ioff. Effect of gate dielectric on the subthreshold performance of the SGOI-TFET is also observed using the Non-Local BTBT model and it is found that the ON current is enhanced with increase in relative permittivity of the gate dielectrics. Synopsys TCAD is used for various optimization of the device which shows the result with the record high Ion/Ioff ratio of 3.4×109 and the steepest average subthreshold swing of 36 mV/ decade. View full abstract»

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  • Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth

    Page(s): 107 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement in the 3-dB bandwidth by introducing an extra stage, consisting of MOS transistors (MOST). The coupling capacitor and a PMOS transistor operating in triode region is connected between the output of the extra stage and the input of the second stage. The simulations were carried out in Cadence VIRTUOSO environment using 0.18 μm CMOS process technology. View full abstract»

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  • Effect of particles and contaminants on the static response of a rectangular MEMS diaphragm due to adverse clean room environment — Simulation studies

    Page(s): 111 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    Fabrication of MEMS based multi-functional devices demands complex integration of several micro-engineered components to perfection. It is therefore critical to ensure that at every stage of fabrication the contaminants or particles that get deposited on the device parts do not have any deleterious effect on the device performance. As most of the MEMS based devices are fabricated in a clean room environment the effects of contaminants on the device performance is assumed to be minimal. Nevertheless, it is important to understand device performance with respect to various clean room parameters such as particulate density, temperature and humidity especially if the device is designed to measure very low values of physical/electrical/mechanical parameters. In this article we will focus on the effect of particulate matter on the static stress response of rectangular diaphragm in a MEMS based pressure sensor. Specifically, the static stress responses of a rectangular MEMS diaphragm subjected to the particulate concentration in ISO-6 class clean room environment is investigated using COMSOL Multi-Physics software. View full abstract»

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