2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

9-11 Dec. 2013

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  • [Front cover]

    Publication Year: 2013, Page(s): c1
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  • [Copyright notice]

    Publication Year: 2013, Page(s): 1
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  • Additional reviewers

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  • Message from chairs

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  • Organizing Committee

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  • Program Committee

    Publication Year: 2013, Page(s):1 - 5
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  • Keynote 1 — Moore's law, programmable logic and reconfigurable systems

    Publication Year: 2013, Page(s): 1
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  • Keynote 2 — Past, current, and future of faster, cheaper, better

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  • Keynote 3 — Extreme scale challenges: Can reconfigurable computing come to the rescue?

    Publication Year: 2013, Page(s): 1
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  • Technical demonstrations session [9 demonstration abstracts]

    Publication Year: 2013, Page(s):1 - 5
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (103 KB)

    The demo will demonstrate the use and capabilities of 9 different software environments and applications. View full abstract»

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  • Papers by sessions

    Publication Year: 2013, Page(s):1 - 7
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  • A delay-based PUF design using multiplexer chains

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (231 KB) | HTML iconHTML

    Physically unclonable functions (PUFs) have been a hot research topic in hardware-oriented security for many years. Given a challenge as an input to the PUF, it generates a corresponding response, which can be treated as a unique fingerprint or signature for authentication purpose. In this paper, a delay-based PUF design involving multiplexers on FPGA is presented. Due to the intrinsic difference ... View full abstract»

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  • A framework for PC applications with portable and scalable FPGA accelerators

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (253 KB) | HTML iconHTML

    This paper presents a novel framework for implementing portable and scalable data-intensive applications on reconfigurable hardware. Instead of using expensive “reconfigurable supercomputers”, we focus our work on standard PCs and PCI-Express extension cards featuring Field-Programmable Gate Arrays (FPGAs) and memory. In our framework, we exploit task-level parallelism by manually pa... View full abstract»

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  • A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2m)

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (266 KB) | HTML iconHTML

    Computing modular multiplication over GF(2m) is often a performance critical operation in cryptographic applications. This paper describes the architecture of a scalable and configurable Montgomery modular multiplier over binary fields. This architecture, implemented on a FPGA platform, aims to reduce the computation time thanks to the pipelining of the datapath. Scalability is achieved... View full abstract»

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  • A hierarchical parallel evolvable hardware based on network on chip

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (270 KB) | HTML iconHTML

    Evolvable Hardware (EHW) is inspired by natural evolution for the automatic design of hardware systems, based on Evolutionary Algorithm (EA). This paper proposed a novel optimization process of evolution system by utilizing a two-level hierarchical parallel algorithm and constructing EHW system into NoC infrastructure. The NoC is specially designed for high-speed reconfigurable hardware. Experimen... View full abstract»

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  • A high performance architecture for computing burrows-wheeler transform on FPGAs

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (475 KB) | HTML iconHTML

    Burrows-Wheeler Transform (BWT) has applications in diverse areas such as compressed string matching, biological sequence analysis, error correction, and channel coding. Numerous efforts have been made to improve the performance of BWT in software and hardware. Its use in real time applications such as deep packet inspection and channel coding requires efficient hardware implementations that must ... View full abstract»

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  • A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (383 KB) | HTML iconHTML

    Programming in embedded systems has always been a challenge. Highly-constrained nature of embedded devices invalidates conventional coding practices. The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer. Embedded security applications are no exceptions. Efficient software implementation of symmetric cryptography primitives such as ... View full abstract»

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  • A restricted dynamically reconfigurable architecture for low power processors

    Publication Year: 2013, Page(s):1 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB) | HTML iconHTML

    Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-efficient processors that map a target program's hot path to a reconfigurable datapath. In this paper, we propose a Control-Flow Driven Data-Flow Switching (CDDS) variable datapath architecture for embedded applications that demand extremely low power consumption in a wide range o... View full abstract»

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  • A robust and low resource FPGA-based stereoscopic vision algorithm

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (811 KB) | HTML iconHTML

    The development of new hardware implementations for stereo vision algorithms requires to establish a balanced trade-off among accuracy, speed and resource consumption requirements. FPGA-based devices allow devising flexible implementations fitting specific applications demands. In this paper, we propose a low resource FPGA-based solution for the calculation of the disparity map in a stereo vision ... View full abstract»

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  • A scalable evolvable hardware processing array

    Publication Year: 2013, Page(s):1 - 7
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (794 KB) | HTML iconHTML

    Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit ... View full abstract»

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  • A VLSI architecture for the QR decomposition based on the MCGR algorithm

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (373 KB) | HTML iconHTML

    This article presents a VLSI (Very Large Scale of Integration) architecture for the QR decomposition (QRD) based on the Modified Complex Givens Rotations (MCGR) algorithm. Being the QRD a fundamental matrix-computation tool for factorizing matrices (matrix decomposition), its vast set of applications is extended to solve several engineering problems in many areas. For example, in the context of Sp... View full abstract»

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  • Accuracy, cost, and performance tradeoffs for floating-point accumulation

    Publication Year: 2013, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (351 KB) | HTML iconHTML

    Set-wise floating point accumulation is a fundamental operation in scientific computing, but it presents design challenges such as data hazard between the output and input of the deeply pipelined floating point adder and numerical accuracy of results. Streaming reduction architectures on FPGAs generally do not consider the floating point error, which can become a significant factor due to the dyna... View full abstract»

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  • Alternative implementations of a fractional order control algorithm on FPGAs

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (255 KB) | HTML iconHTML

    Traditionally, microprocessor and digital signal processors have been used extensively in controlling simple processes, such as direct current motors. The Field Programmable Gate Arrays (FPGA) are currently emerging as an alternative to the previously used devices in controlling all sorts of processes. The fractional order proportional-integrative control algorithm has the advantage of enhancing t... View full abstract»

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  • An effective window based legalization algorithm for FPGA placement

    Publication Year: 2013, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (555 KB) | HTML iconHTML

    Placement is one of the most important techniques in modern field-programmable gate array design. Generally, analytical placement method optimizes the wire-length in global stage while allowing overlaps between blocks and is followed by a legalization step to remove all overlaps. In this paper, we propose a window based legalization method to remove all overlaps and place all instances at legalize... View full abstract»

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  • An efficient application-specific instruction-set processor for packet classification

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (330 KB) | HTML iconHTML

    Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls and traffic billing, just to name a few. However, classification can be a bottleneck in the above mentioned applications if not implemented properly and efficiently. In this paper we propose an Application Specific Instruction Processor (ASIP) implementation for the PCIU (Packet Clas... View full abstract»

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