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Field-Programmable Technology (FPT), 2013 International Conference on

Date 9-11 Dec. 2013

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Displaying Results 1 - 25 of 118
  • [Title page]

    Publication Year: 2013 , Page(s): 1
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  • [Copyright notice]

    Publication Year: 2013 , Page(s): 1
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  • Message from the general chair and program co-chairs

    Publication Year: 2013 , Page(s): 1
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  • Organization

    Publication Year: 2013 , Page(s): 1 - 2
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  • Contents

    Publication Year: 2013 , Page(s): 1 - 6
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  • Keynote lectures [breaker page]

    Publication Year: 2013 , Page(s): 1
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  • Recent advances in die stacking and 3D FPGA

    Publication Year: 2013 , Page(s): 1
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  • Reconfigurable chip advantage compared with GPGPU from the compiler perspective

    Publication Year: 2013 , Page(s): 2
    Cited by:  Papers (1)
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  • Why Put FPGAs in your CPU socket?

    Publication Year: 2013 , Page(s): 3
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  • 1.1 Best paper candidate session

    Publication Year: 2013 , Page(s): 1
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  • Accelerating validation of time-triggered automotive systems on FPGAs

    Publication Year: 2013 , Page(s): 4 - 11
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    Automotive systems comprise a high number of networked safety-critical functions. Any design changes or addition of new functionality must be rigorously tested to ensure that no performance or safety issues are introduced, and this consumes a significant amount of time. Validation should be conducted using a faithful representation of the system, and so typically, a full subsystem is built for val... View full abstract»

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  • Exploiting partially defective LUTs: Why you don't need perfect fabrication

    Publication Year: 2013 , Page(s): 12 - 19
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    Shrinking integrated circuit feature sizes lead to increased variation and higher defect rates. Prior work has shown how to tolerate the failure of entire LUTs and how to tolerate failures and high variation in interconnect. We show how to use LUTs even when they are partially defective - a form of fine-grained defect tolerance. We characterize the defect tolerance of a range of mapping strategies... View full abstract»

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  • Maximum flow algorithms for maximum observability during FPGA debug

    Publication Year: 2013 , Page(s): 20 - 27
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (558 KB) |  | HTML iconHTML  

    Due to the ever-increasing density and complexity of integrated circuits, FPGA prototyping has become a necessary part of the design process. To enhance observability into these devices, designers commonly insert trace-buffers to record and expose the values on a small subset of internal signals during live operation to help root-cause errors. For dense designs, routing congestion will restrict th... View full abstract»

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  • The architecture and placement algorithm for a uni-directional routing based 3D FPGA

    Publication Year: 2013 , Page(s): 28 - 33
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1189 KB) |  | HTML iconHTML  

    Three-Dimensional (3D) FPGA as a promising design trend, achieves significant performance improvement over conventional 2D-based FPGA. The maturity of the uni-directional routing architecture design, which achieves 25% area saving in area-delay-product (ADP) over bi-directional routing architectures, has driven major vendors such as Xilinx and Altera to switch to such architecture in their 2D-base... View full abstract»

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  • 1.2 Architecture

    Publication Year: 2013 , Page(s): 1
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  • COFFE: Fully-automated transistor sizing for FPGAs

    Publication Year: 2013 , Page(s): 34 - 41
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    In this paper, we present COFFE (Circuit Optimization For FPGA Exploration), a new fully-automated transistor sizing tool for FPGAs. Automated transistor-level CAD tools are an important part of the architecture exploration flow because they provide accurate area and delay estimates of low-level FPGA circuitry, which must be obtained for each architecture. We show that modeling transistors as line... View full abstract»

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  • A case for hardened multiplexers in FPGAs

    Publication Year: 2013 , Page(s): 42 - 49
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    This paper presents a case for a hybrid configurable logic block that contains a mixture of LUTs and hardened multiplexers towards the goal of higher logic density and area reduction. Technology mapping optimizations, called MuxMap, that target the proposed architecture are implemented using a modified version of the mapper in the ABC logic synthesis tool. VPR is used to model the new hybrid confi... View full abstract»

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  • Debugging processors with advanced features by reprogramming LUTs on FPGA

    Publication Year: 2013 , Page(s): 50 - 57
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (630 KB) |  | HTML iconHTML  

    In this paper, we propose an automated method for debugging and rectification of logical bugs in processors that are implemented on FPGAs. Our method is based on preserving the current circuit topology, and debugging and rectifying bugs by only changing the contents of LUTs, without any modification to the wiring. As a result, correcting the bugs does not require re-synthesis, which can be very ti... View full abstract»

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  • 1.3 FPGA applications I

    Publication Year: 2013 , Page(s): 1
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  • Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

    Publication Year: 2013 , Page(s): 58 - 65
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1729 KB) |  | HTML iconHTML  

    We developed a custom FPGA-based Network Interface Controller named APEnet+ aimed at GPU accelerated clusters for High Performance Computing. The card exploits peer-to-peer capabilities (GPU-Direct RDMA) for latest NVIDIA GPGPU devices and the RDMA paradigm to perform fast direct communication between computing nodes, offloading the host CPU from network tasks execution. In this work we focus on t... View full abstract»

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  • Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs

    Publication Year: 2013 , Page(s): 66 - 73
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    Iterative algorithms represent a pervasive class of data mining, web search and scientific computing applications. In iterative algorithms, a final result is derived by performing repetitive computations on an input data set. Existing techniques to parallelize such algorithms typically use software frameworks such as MapReduce and Hadoop to distribute data for an iteration across multiple CPU-base... View full abstract»

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  • High throughput, tree automata based XML processing using FPGAs

    Publication Year: 2013 , Page(s): 74 - 81
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    A novel and efficient approach to XML processing using FPGAs, based upon the sound theoretical formalism of tree automata, is presented. The approach enables the key tasks of schema validation and query to be performed in a unified manner. A remarkably simple implementation of a tree automaton in hardware, as a pair of interacting automata with the states of one forming the input to the other, is ... View full abstract»

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  • Transparent FPGA based device for SQL DDoS mitigation

    Publication Year: 2013 , Page(s): 82 - 89
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    A Distributed Denial-of-Service attack is an attempt to make a computer resource unavailable to its intended users. Typically, a large number of bots are triggered by an attacker simultaneously to create a huge load on a web server and bring it down. However, when processing SQL queries on a web server, owing to huge resource requirements, even a small number of queries from smaller set of bots ca... View full abstract»

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  • 1.4 Power-aware and dynamically reconfigurable systems

    Publication Year: 2013 , Page(s): 1
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  • Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems

    Publication Year: 2013 , Page(s): 98 - 105
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1237 KB) |  | HTML iconHTML  

    Discrete event system specification (DEVS) has been widely used within modeling and simulation to design, verify, and implement complex reactive systems. DEVS provides a robust formalism for designing systems using event-driven, state-based models in which timing information is explicitly defined. In this paper, we present an overview of a DEVS-based hardware design, synthesis, and optimization me... View full abstract»

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