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Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Date 16-16 Dec. 1998

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Displaying Results 1 - 25 of 76
  • Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)

    Publication Year: 1998
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    Freely Available from IEEE
  • A 1.5 V 3rd-order fully-differential CMOS Gm-C filter with micropower class-AB V-I converters

    Publication Year: 1998 , Page(s): 208 - 210
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    A 3rd-order fully-differential continuous time elliptic filter is presented which is composed of widely-linear input V-I converters with a minimum supply voltage of 1.5 V and 1% THD for rail-to- rail input swing. In a 1.2 μm n-well CMOS process, this filter can achieve 3dB frequency of 163 kHz with only 138 μW power dissipation at 1.5 V supply voltage. THD with 50 kHz 1Vpp fully-differential input signal is 1.8% View full abstract»

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  • Efficient method for large signal distortion minimization of field effect transistor circuits

    Publication Year: 1998 , Page(s): 219 - 222
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    Prediction of distortion effects is an important aspect in high frequency systems design. In this paper, we present a method which minimizes the intermodulation products of transistors. Based on the characteristic surface method the technique consists to determine the optimum harmonic loads for the active elements and then, using Volterra series, to minimize the intermodulation powers. The validity of the proposed method was confirmed by comparing the computed values with these presented in technical literature View full abstract»

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  • Programmable current source dedicated to implantable microstimulators

    Publication Year: 1998 , Page(s): 67 - 70
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    In this paper, a survey of programmable current-source architectures based on miniaturized digital-to-analog converters (DAC) is elaborated to propose a new design dedicated to a visual microstimulator. The needed current-source constitutes the electronic interface to tissues. A few samples of this current-source will be integrated in an implantable device which is powered and controlled using an electromagnetic coupling technique. The main objective is to select a design that meets as close as possible criteria related to the implant such as reliability, flexibility, energy efficiency and integration area. Consequently, an adequate current source is proposed which is a 5-bit thermometer-code-based DAC architecture. The resulting circuit is simulated using a 0.35 μm CMOS technology from PMC-Sierra available through the Canadian Microelectronics Corporation (CMC) View full abstract»

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  • Effect of the selection MOS transistor polarization voltage during a write and an erase operation of an EEPROM memory cell

    Publication Year: 1998 , Page(s): 149 - 152
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    The use of EEPROM memory cells has covered in the last years a wide range of applications. These are of analog and mixed type. In order to improve the good behavior and the exploration of new applications, the development of an efficient and compact EEPROM memory cell model seems to be a necessity. Previous studies usually focused on the floating gate MOS transistor performance without knowledge of the selection MOS transistor effect during real functioning of a cell in an EEPROM matrix. This paper is a first approach to the evaluation of the select gate voltage variations effect on memory cell performance View full abstract»

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  • Artificial neural networks applications in problems of fitting in forestry

    Publication Year: 1998 , Page(s): 170 - 173
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    Neural networks with different architectures and different activation functions represent a powerful tool for solving many approximation problems. Combining the knowledge of a forestry theory with the empirical knowledge stored in an artificial neural networks (ANN) trained on examples, can bring very significant results with respect to traditional approaches. In our example neural networks represent a very powerful tool for solving problems of a fitting in forestry View full abstract»

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  • A parallel technique for ATPG using genetic algorithms

    Publication Year: 1998 , Page(s): 71 - 73, 74a-c
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    This paper presents a new technique for test pattern generation based on a genetic algorithm and parallel processing techniques. This new method offers compact test sets, compared to other methods, that achieve maximum coverage View full abstract»

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  • Time-frequency speech processing strategy based on an adjustable algorithms dedicated to the cochlear prostheses

    Publication Year: 1998 , Page(s): 245 - 248
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    Cochlear implants are electronic devices designed to provide useful hearing and improved communication ability to individuals who are profoundly hearing impaired and unable to achieve speech understanding with hearing aids. For individuals with a profound hearing loss, even the most powerful hearing aids may provide little to not benefit. A profoundly deaf ear is typically one which the majority of sensory receptors in the inner ear, called hair cells, are damaged or diminished. Cochlear implants bypass damaged hair cells and directly stimulate the residual hearing nerves with electrical current, allowing individuals who are profoundly or totally deaf to receive sound View full abstract»

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  • High performance balanced current controlled amplifiers

    Publication Year: 1998 , Page(s): 183 - 186
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    High performance balanced current controlled voltage-mode amplifiers are presented. They are constituted of four class AB controlled conveyors and do not require any external passive component. They are easily tunable from the bias currents which give to them a good versatility. These fully differential amplifiers provide wide bandwidth, low harmonic distortion and very low output offset voltage View full abstract»

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  • The microelectronics initiatives in Egypt

    Publication Year: 1998 , Page(s): IP18 - IP21
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    This paper presents a proposal to establish a VLSI components industry in Egypt. The first stage has been started in the Electron Factory owned by the Arab Industrial Authority (AIA). In the mean time a study to start the second stage is underway. The Microelectronics Research Center with the Faculty of Engineering Ain Shams University and the Electronics Research Institute with the Egyptian Academy of Science and Technology are helping the factory in conducting this study View full abstract»

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  • A BiCMOS wide-lock range fully integrated PLL

    Publication Year: 1998 , Page(s): 274 - 277
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A fully integrated Phase Locked Loop (PLL) with wide lock range is presented in this paper. The designed structure of the PLL is based on the charge-pump type with a differential architecture Voltage Controlled Oscillator (VCO) building block. In the proposed VCO, current mirrors are used as the active load of the source-followers which allow a high stability of VCO oscillation within a wide control range. The PLL has been implemented in 0.8 μm BiCMOS technology without the need of any external components. It operates with a lock range of 14 to 420 MHz. The lock time is 15 μS. The resulting layout area and the power dissipation of the whole PLL are 0.65 mm2 and 18 mW respectively View full abstract»

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  • Low power CMOS digital design

    Publication Year: 1998 , Page(s): IP6 - I13
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity). In a second part, the paper will show the incidence of scaling down the transistors on power dissipation. The third part will address the question: what is performance. Next, the fourth part will discuss complexity versus dissipation and finally glitch filtering View full abstract»

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  • Benefits of HLS and rapid prototyping in the integrated complex circuits design loop

    Publication Year: 1998 , Page(s): 253 - 256
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    In this paper, we propose an integrated circuit application based on high level specification of VHDL description. This presentation gives a comprehensive description of different synthesis steps using a design of a real time example: the Multi-Recommendations-Modem (MRM). The design flow includes all steps from High Level Synthesis up to rapid prototyping. In this respect, architectural, logical and physical synthesis are performed in the synthesis steps. The application consists of the securing implementation function of a MRM in emission mode. The system includes three hardware parts: encoder, digital modulator and synchronization signal generator View full abstract»

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  • Low energy implantation and transient enhanced diffusion: a reliable approach to secondary defect profile measurements

    Publication Year: 1998 , Page(s): 119 - 122
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    It is well known that low energy implantation is the most promising option for ultra shallow junction formation in the next generation of silicon BiCMOS technology. Among the dopants that have to be implanted, boron is the most problematic because of its low stopping power and its tendency to undergo transient enhanced diffusion and clustering during thermal activation. This paper reports an experimental contribution with the help of secondary defect profiles to our understanding of low energy B implants in crystalline silicon. Shallow p +n junctions were formed by low energy B implantation-1015 cm-2 at 3 keV-into a n-type monocrystalline silicon preamorphized with germanium. Rapid thermal annealing for 15 s at 950°C was then used for dopant electrical activation and implantation damage removal. A reliable approach using the secondary defect profiles induced by this process, measured with isothermal transient capacitance in association with deep level transient spectroscopy is proposed. A relatively high concentration of B-related electrically active defects have been obtained up to 3.5 μm into the crystalline silicon bulk View full abstract»

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  • A novel Q tuning method, using variable output conductance of transconductors

    Publication Year: 1998 , Page(s): 191 - 194
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    In this paper, the effects of Transconductors' phase shifts on the Q factor of a second order system are discussed and it is shown that this negative phase shift appears as negative conductance in an integrator and amount of this conductance can be achieved in a general filter. A new Q tuning method based on compensation of this phase shift by variable output conductance of Transconductors is applied and simulated results are shown View full abstract»

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  • A digital control system based on codesign technology

    Publication Year: 1998 , Page(s): 257 - 261
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    In recent years, the ever-increasing capabilities of microelectronic devices allow the implementation of more sophisticated speed drives. The control structure performs a greater number and a wider range of functions. The difference in the nature of these functions pushed the designer to investigate the architecture on the hand, and the implementation on the other hand. A control system implemented on Codesign technology allows the use of the advantages of DSP in numerical calculation and FPGA in logical computation. The definition of system (FPGA and DSP) is reviewed and the reasons for this choice are discussed. The advantages of this technology are discussed as well as the difficulties encountered at the development stage View full abstract»

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  • Design and chip implementation of modified CORDIC algorithm for Sine and Cosine functions application: PARK transformation

    Publication Year: 1998 , Page(s): 241 - 244
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The CO-ordinate Rotation DIgital computer (CO.R.DI.C) algorithm is an iterative procedure to evaluate various elementary functions. In this contribution, design and chip implementation of modified CORDIC algorithm for sine and cosine are presented. Modified CORDIC algorithm reduce the number of iterations. The modified algorithm needs, at most, half the number of iterations to achieve the same accuracy as the classical algorithm. The modifications are applicable to circular CORDIC in rotation modes. The hardware integration is carried out using field programmable gate arrays (F.P.G.As). To demonstrate the performances of the design, pipeline architecture of the CORDIC algorithm is studied. The design is used to compute the PARK transformation in control theory for electric vehicle View full abstract»

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  • A low-voltage current-controlled oscillator with low supply dependency

    Publication Year: 1998 , Page(s): 282 - 285
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A new current-controlled oscillator (CCO) is presented which is suitable for use in low-voltage and low-power designs. These features, and the low supply dependence of this CCO all stem from using a regenerative mechanism in its primitive delay cells. The circuit is designed and simulated in a 0.8 μm BiCMOS technology View full abstract»

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  • Towards system level design methodology for dedicated telecommunication systems

    Publication Year: 1998 , Page(s): IP14 - IP16, 2
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    Telecommunication systems design and prototyping present a wide range of features such as fast product evolution and upgrading, embedded design constraints (low power, etc.), the increasingly complexity growing of norms and a real need of flexibility for open norms systems (MPEG4, UMTS, etc.). So, designers should have new design methodologies skills to perform at the same time systems design validation and mastering the sub-micronic technological integration constraints. This paper reviews design methods and trends for telecommunication systems View full abstract»

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  • A robust neural network multi-lane recognition system

    Publication Year: 1998 , Page(s): 178 - 182
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    In this paper, the design and neural implementation of a vision based multi-lane highway lane recognition system are presented. The design objective of the system is to recognize the lane which a test vehicle is currently driving through by determining its left and right lane boundaries. When the proposed lane recognition system was tested it showed very high percentage of correct results in very difficult circumstances which suggests that it provides the basis for a reliable road following system View full abstract»

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  • A 1.5-V current-mode capacitance multiplier

    Publication Year: 1998 , Page(s): 9 - 12
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    In this work the problem of obtaining capacitance values higher than those normally integratable and/or provided by capacitive transducers has been investigated. The solution here proposed consists of a capacitance multiplier made up of a current conveyor and a current operational amplifier which allows accurate capacitance factors up to 100 to be achieved. Moreover, thanks to the use of the current mode approach, low supply voltage operations (profitable in portable sensor systems) are obtained. The whole topology has been designed in a standard 0.5-μm CMOS technology with a 1.5-V supply voltage and micropower consumption. SPICE simulations show a good agreement with the expected results and confirm an accurate multiplication factor for capacitances higher than 1 pF View full abstract»

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  • Statistical design of the four-MOSFET structure

    Publication Year: 1998 , Page(s): 228 - 231
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    The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through the contours. Yield enhancement and optimization of transistor W and L values are demonstrated. (Experimental results will be provided at the conference) View full abstract»

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  • Photoluminescence spectra of doped and undoped CdS films prepared by spray pyrolysis

    Publication Year: 1998 , Page(s): 127 - 130
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    Large area thin films of n-type CdS:In were prepared by spray pyrolysis technique. The films were n-type doped by having |In/Cd| ion concentration ratio of 10-6, 10-5, 10-4, 10-3, and 10-2 in the sprayed solution. These films were heat treated in N2 atmosphere at 450°C for one hour. The as deposited undoped, doped, and heat treated films were analyzed by photoluminescence (PL) at 5 K sample temperature. In general, the spectra displayed three main emission regions (green, yellow and red) with more than one band in each. The emission intensity is found to decrease with doping and the relative intensity of the bands is found to depend on the doping concentration level. The red band is only present in doped samples and its relative intensity is found to increase with doping. The effect of heat treatment in N2 on the as deposited undoped and the doped (10-4 ) samples on the relative intensity of the observed bands were compared and discussed. The results are compared with the electrical and morphological results and correlated with the probable changes in the concentration of shallow and deep radiative native defects and structural changes. These allow for better prediction of suitable doping and treatment conditions for good quality films View full abstract»

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  • Reduced bond graph modeling of semiconductor device thermal effects

    Publication Year: 1998 , Page(s): 135 - 140
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    Faced with the problem of modeling complex and mixed-domain dynamic systems, system engineers use the bond graph formalism. Bond graph techniques are now used for modeling semiconductor devices in power electronics field. To have accurate models of power devices, it is necessary to take into account the thermal phenomena modeled by a thermal network. The thermal network describes the heat flow and the temperature evolution from the chip surface through the package and heat sink. To model these semiconductor devices, the bond graph model of the thermal and electrical parts must be described to illustrate how they are coupled, in order to build the device electrothermal model. In this paper, regardless of the switch state, the bond graph formalism application to power semiconductor devices, combining the electrical and thermal phenomena, is presented. A reduction procedure application to the semiconductor device thermal effects is also proposed in order to obtain a reduced electrothermal bond graph model View full abstract»

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  • Simple multifunction filter realizations with current conveyors

    Publication Year: 1998 , Page(s): 204 - 207
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A new current conveyor based filter topology with two different realisation possibilities using only positive type second generation current conveyors and only grounded passive components is presented. For both possibilities no element matching conditions are imposed. The filters permit orthogonal adjustment of quality factor Q and resonant angular frequency ω0. The circuits exhibit high input impedance thus enable easy cascadability. The passive sensitivities are shown to be low. The functionality of one of the circuits is tested on a filter design example by experiment View full abstract»

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