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Semiconductor Conference (CAS), 2013 International

Date 14-16 Oct. 2013

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  • Front and back cover

    Publication Year: 2013 , Page(s): c1 - c4
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  • Title page

    Publication Year: 2013 , Page(s): 1
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  • Copyright page

    Publication Year: 2013 , Page(s): 1
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  • Sponsor page

    Publication Year: 2013 , Page(s): 1
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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  • Foreword

    Publication Year: 2013 , Page(s): v
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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  • Organizing committee

    Publication Year: 2013 , Page(s): vii - viii
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  • Contents

    Publication Year: 2013 , Page(s): ix - xv
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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  • Author index

    Publication Year: 2013 , Page(s): xvii - xviii
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  • Session D: Semiconductor devices

    Publication Year: 2013 , Page(s): 1
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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  • On the variation of the 2DEG charge density with the density of the surface donor traps in AiGaN/GaN transistors

    Publication Year: 2013 , Page(s): 155 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (941 KB) |  | HTML iconHTML  

    Gallium nitride (GaN) has a bright future in high voltage device owing to its remarkable physical properties and the possibility of growing heterostructures on silicon substrates. GaN High Electron Mobility Transistors (HEMTs) are expected to make a strong impact in off line applications and LED drives. However, unlike in silicon-based power devices, the on-state resistance of HEMT devices is hugely influenced by donor and acceptor traps at interfaces and in the bulk. This study focuses on the influence of donor traps located at the top interface between the semiconductor layer and the silicon nitride on the 2DEG density. It is shown through TCAD simulations and analytical study that the 2DEG charge density has an `S' shape variation with two distinctive `flat' regions, wherein it is not affected by the donor concentration, and one linear region. wherein the channel density increases proportionally with the donor concentration. We also show that the upper threshold value of the donor concentration within this `S' shape increases significantly with the AIGaN thickness and the Al mole fraction and is highly affected by the presence of a thin GaN cap layer. View full abstract»

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  • New Beta-Matrix topology in CMOS32nm and beyond for ESD/LU improvement

    Publication Year: 2013 , Page(s): 159 - 162
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1159 KB) |  | HTML iconHTML  

    This paper is focused on the optimization of Beta-Matrix power device to protect thin oxide GO1 =1 V and thick oxide G02=1.8V. The study investigates Beta-Matrix topology and particularly the impact of elementary pattern on device behavior. This work is mainly carried on 3D TCAD simulations. The best configurations, with lower voltage triggering have been realized in CMOS32nm high k metal gate and characterized thanks Transmission Line Pulse (TLP) with 100ns width. View full abstract»

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  • 4H-SiC Schottky contact improvement for temperature sensor applications

    Publication Year: 2013 , Page(s): 163 - 166
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (947 KB) |  | HTML iconHTML  

    An improvement in performance of 4H-SiC Schottky diodes using a Ni metal is proposed. The effects of the Schottky and ohmic contacts' annealing process conditions are investigated through electrical characterization of the diodes. A thermal treatment at 800°C leads to devices with stable and reproducible electrical behavior. A high performance temperature sensor based on these 4H-SiC Schottky diode has been proved. View full abstract»

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  • ESD protection with BIMOS transistor for bulk & FDSOI advanced CMOS technology

    Publication Year: 2013 , Page(s): 171 - 174
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1266 KB) |  | HTML iconHTML  

    The purpose of this paper is to introduce the ESD protection using BIMOS transistor in bulk CMOS and in hybrid area for 28nm FDSOI High k metal gate. Moreover the DC behavior is also performed. Thus, this study introduces an ESD protection with a minimum of silicon area consumption and efficient to protect the MOS transistors with thin & thick oxide and also in thin silicon film. TCAD simulations are done in 2D and 3D with classical equation of semiconductor. Moreover, all results are done through silicon measurements on demonstrator devices. View full abstract»

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  • Session IC1: Integrated circuits 1

    Publication Year: 2013 , Page(s): 1
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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  • RF power potential of High-k metal gate 28 nm CMOS technology

    Publication Year: 2013 , Page(s): 181 - 184
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    This paper reports on the first RF microwave power characterization of High-k metal gate 28 nm CMOS devices. Measurement was performed on Load-pull configuration using a Nonlinear Vector Network Analyzer (NVNA) associated with a passive tuner at the fundamental frequency of 10 GHz. Behavior of these High-k metal gate 28 nm CMOS was analyzed on large signal conditions in class A operation. The maximal drain voltage withstanding was determined for various topologies. Transistors behavior was analyzed for optimal load impedance condition in terms of microwave output power and power added efficiency. Finally, a comparison with the standard 45 nm CMOS was achieved. View full abstract»

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  • Soft-start low voltage CMOS LDO

    Publication Year: 2013 , Page(s): 185 - 188
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    The paper presents a soft-start low voltage CMOS LDO. A double-reference bandgap was developed to provide the soft-start feature. The first reference is quicker and drives the start-up circuit, while the second is slower and, after being divided, drives the LDO core. This circuit technique allows the reduction of the supply voltage and the control of the output voltage rise time through an external capacitor in order to reduce the inrush current at start-up. Also, there is no overshoot on the output voltage at start-up, even for large capacitive loads. View full abstract»

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  • Comparative study of two LDOs for supplying a 2.5GHz rail-to-rail VCO

    Publication Year: 2013 , Page(s): 189 - 193
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1444 KB) |  | HTML iconHTML  

    This paper presents a comparative study of two low dropout voltage regulators (LDO) for supplying a 2.5GHz rail-to-rail voltage controlled oscillator (VCO). The effect of the two LDOs noise on the phase noise of the VCO is presented while keeping the supply ripple the same. Both LDO structures are implemented by using the same error amplifier and the same pass transistor, but the classical LDO uses a large off chip decoupling capacitor while the capacitorless LDO employs a current amplifier which forms high bandwidth around the pass transistors to reduce the supply ripple. Post layout simulation results show a -88dBc/Hz and -83dBc/Hz VCO phase noise at 1MHz for the classical and capacitorless LDO. The LDOs and the VCO were designed in 0.18μm CMOS process. View full abstract»

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  • Determining the optimal number of gain stages of variable gain amplifiers used in multi-standard homodyne wireless receivers

    Publication Year: 2013 , Page(s): 193 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (647 KB) |  | HTML iconHTML  

    This paper presents an analysis on determining the optimal number of gain stages of Variable Gain Amplifiers (VGAs) used in direct conversion CMOS multi-standard wireless receivers embedding analog baseband signal conditioning. In order to facilitate design porting, modern re-configurable wireless receivers are based on a modular architecture for the low frequency part of their analog signal conditioning chain, which includes also the VGA. The analysis constructed in this paper determines the optimal number of VGA stages as the solution of the trade-off between the stage amplifier's power consumption and its linearity performance. Based on the presented analysis it results a VGA embedding 7 stages is able to achieve 84 dB gain range and it represents the best choice with respect to optimizing both the VGA power consumption and its linearity performance. View full abstract»

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  • Session IC2: Integrated circuits 2

    Publication Year: 2013 , Page(s): 1
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  • Blank page

    Publication Year: 2013 , Page(s): 1
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