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Thermal Investigations of ICs and Systems (THERMINIC), 2013 19th International Workshop on

Date 25-27 Sept. 2013

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Displaying Results 1 - 25 of 77
  • Analysis of the effectiveness of core swapping in modern multicore processors

    Page(s): 385 - 388
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (825 KB) |  | HTML iconHTML  

    One of the interesting thermal management techniques for multi-core processors is core swapping. In this paper, using the published power data and floorplans for two modern high-performance processors, we employ the well-known HotSpot tool to perform the thermal simulation of the core swapping mechanism. Our transient simulations show that by using core swapping technique, it was possible to either minimize the hot spot temperature in the Ivy Bridge chip by 5°C or increase the operating frequency by 17% and maintain the same temperature as in the case without core swapping. We also derive an analytical model of the activity migration mechanism between two cores which may serve as a tool to calculate the swapping frequency given the desired maximal temperature drop. The model also allows for the correlation of the cooling effectiveness with the performance penalty induced by the swapping. View full abstract»

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  • Approach for reliability of Thermal Interface Materials in battery cell sensors

    Page(s): 348 - 351
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    In battery packs it is important to know, which temperature the cells have, to avoid overloads and damages. A temperature sensor, which is joined on the battery cell, delivers such data. To guarantee exact temperature measurements on the cell, reliable Thermal Interface Materials (TIM) are needed. They ensure heat transfer from battery cell to the sensor and need to provide good thermal conductivity, moisture independence and adhesion performance under combined environmental loads. For these requirements three different TIM materials were tested and analyzed to determine defects and observing degradation processes under cyclic temperature and moisture loads. Also on focus are the selection guidelines of the correct TIM for different application. The paper describes the characterization of different TIMs, new thermal test cycles combined with moisture and the resulting effects on degradation behavior of TIMs. View full abstract»

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  • Author index

    Page(s): 1 - 3
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    Freely Available from IEEE
  • Characterization and kinetic monitoring of the reactions between TixAly phases in Ti-Al based ohmic contacts on n-type GaN by Differential Scanning Calorimetry (DSC)

    Page(s): 372 - 375
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    This work reports on DSC measurements performed on Ti-Al metallic layers stacks deposited on n+-GaN. The aim is to get better understanding of the mechanisms leading to ohmic contact formation during the annealing stage. Two exothermic DSC peaks were found : one below 500°C and the other one around 660°C. They can be respectively attributed to Al3Ti and Al2Ti compounds formation. Lowest contact resistance is well correlated with the presence of Al3Ti compound, corresponding to Al(200nm) / Ti(50nm) stoichiometric ratio. Subsequently, Al (200 nm) / Ti(50 nm) stacks on n+-GaN were comparatively annealed from 400 °C to 650 °C. Specific Contact Resistivity (SCR) values stay in the mid 10-5 Ω.cm2 range for annealing temperatures between 450 °C and 650 °C. Such low-temperature annealed contacts on n+-GaN may open new device processing routes, simpler and cheaper, in which Ohmic and Schottky contacts are annealed together. View full abstract»

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  • Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs

    Page(s): 237 - 242
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    In this paper, we investigate the co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. The architecture is a 16 core, x86 multicore die stacked with a second die hosting an L2 SRAM cache. First, a multicore x86 compatible cycle-level microarchitecture simulator was constructed and integrated with physical power models. The simulator executes benchmark programs to create power traces that drive thermal analysis. Second, the thermal characteristics under liquid cooling were investigated using a compact thermal model. Four alternative packaging organizations were studied and compared. Greatest overall temperature reduction is achieved under a given pumping power, with two tiers and two microgaps with the high power dissipation tier on the top. Third, an optimization of the pin fin parameters including the diameter, height, and longitudinal and transversal spacing was performed. This optimization is shown to achieve up to 40% improvement in energy/instruction and significant reductions in leakage power. View full abstract»

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  • Combined method for thermal characterization of high power semiconductors

    Page(s): 341 - 343
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    Commonly computational methods are used to determine and enhance the lifetime of electronics and electronic systems. The validity of such methods highly depends on the used material data and therefore on the quality of the accompanying experiments. For this reason different methods were combined to better determine the thermal state of a desired device of variable size, while providing this data within in a reasonable short time. The method allows the in-situ measurement of: · the surface temperature of the top and bottom side by IR thermography and a steady state technique · the junction temperature using transient method · the generated heat flow by the tested device The correlating temperatures of the heating and cooling phase can be monitored at different geometries and setups which allows to build up static and transient simulation models and therefore make the reliability assessment of the used setup or device for many application cases possible. View full abstract»

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  • Compact electro-thermal models of interconnects

    Page(s): 309 - 314
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    In this paper a novel approach is proposed for generating nonlinear compact models of the dynamic electrothermal problems modeling interconnects. The method is very efficient and leads to accurate approximations of the space-time distribution of voltages, currents and temperature rises within the interconnects for all waveforms of the port variables. View full abstract»

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  • Controlling the density of CNTs by different underlayer materials in PECVD growth

    Page(s): 248 - 252
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    In this paper, we present a new approach of controlling the growth density of carbon nanotubes (CNTs) by controlling the thickness of Cu underlayer. Tested thicknesses of Cu range from 5nm to 150nm. In this work, we have tried two kinds of barrier layer material, namely Mo and Al2O3 against the diffusion of Ni catalysts. The results suggest Al2O3 is a better barrier layer material and more suitable than Mo to be applied with Cu underlayer for the controlling of growth density of CNTs. In the end, this paper also gives a tentative explanation of this new method of controlling CNT growth density by adjusting the thickness of Cu underlayer. View full abstract»

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  • Convolution based compact thermal model for 3D-ICs: Methodology and accuracy analysis

    Page(s): 152 - 157
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    Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging [1]. Compact thermal models (CTM) are being developed for fast evaluation of the thermal distribution in the 3D packages. The CTM discussed in this paper is based on the Green's function theory and exploits convolution and fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. Detailed accuracy assessments are presented for the grid size and for the number of images to be considered for an accurate modelling of the lateral insulating boundary conditions. A two dies stack case study is also analysed showing good agreement with the finite element model results (error less than 0.5%). Finally, the algorithm computational time is discussed indicating a O(N logN) behaviour where N is the number of elements in the matrices. View full abstract»

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  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • Development and fabrication of a thin film thermo test chip and its integration into a test system for thermal interface characterization

    Page(s): 67 - 72
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    This paper deals with the development und fabrication of a thermal test chip (TTC) to be used for thermal characterisation and qualification of materials and packages. The TTC is designed as a modular chip with the smallest full functional chip cell of 3.2mm × 3.2mm and consists of a heater structure and a temperature sensor. The chips can be applied in any required matrix. Heater and temperature sensors are realised by a 70 nm single Titanium layer as adhesion and barrier layer. The Titanium is structured a on 670μm silicon wafer by the cost efficient thin film technology. 3×3 matrix chips have been sawn, assembled on a FR4 substrate by flip chip technology and integrated into a test stand for characterisation of thermal interface materials (TIMA Tester). The calibration curves of the temperature sensors show 4-time higher sensitivity then Si diodes. The homogeneity of the surface temperature was checked by the Lock-In infra-red thermography and compared with a commercial thermo test chip. View full abstract»

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  • Double-sided cooling and thermo-electrical management of power transients for silicon chips on DCB-substrates for converter applications: Design, technology and test

    Page(s): 253 - 261
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    This paper deals with the system design, technology and test of a novel concept of integrating Si and SiC power dies along with thermo-electric coolers in order to thermally manage transients occurring during operation. The concept features double-sided cooling as well as new materials and joining technologies to integrate the dies such as transient liquid phase bonding/soldering and sintering. Coupled-field simulations are used to predict thermal performance and are verified by especially designed test stands to very good agreement. This paper is the second in a series of publications on the ongoing work. View full abstract»

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  • Dynamic sub-compact model and global compact model reduction for multichip components

    Page(s): 158 - 163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6958 KB) |  | HTML iconHTML  

    The trend at the level of electronic component is to gather several active chips inside the same enclosing package. The thriving development of this technology allows reducing the volume in space as well as shortening the interconnection between the elements of the device. In this article, we analyze two methods of reduction of a detailed representation of a component, embedding three chips. The first approach is based upon the sub-compact vision, which consists in generating thermal compact models of different pseudo parts and plugged them within the over-molding resin of the package. This one gives good results but the size of the deducted model remains large. The second way uses a global reduction process by generating a whole network at once by means of genetic algorithm and superposition principle. The predictions of the behavioral models are relevant, poorly dependant of boundary conditions but the number of mandatory fitting scenarios becomes quite significant as well as the parameters to be optimized. View full abstract»

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  • Effect of nanostructuration on the thermal conductivity of thermoelectric materials

    Page(s): 73 - 78
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    We have investigated various kinds of nanowires (Si, Bi2Te3, SiGe) in order to evaluate the influence of the nanostructuration on their thermal conductivity. The method used is a 3ω-SThM (Scanning Thermal Microscopy) technique which enables to simultaneously measure the topography and the thermal conductivity on an assembly of NWs. We detail the procedure from the measurement itself to the nanowire thermal conductivity estimation. We show that the nanostructuration leads to a thermal conductivity reduction for the 3 materials we have studied and that Si and SiGe nanowire samples seem more promising than Bi2Te3 NWs in terms of thermoelectric applications. View full abstract»

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  • Electro-thermal co-design of chip-package-board systems

    Page(s): 361 - 367
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2177 KB) |  | HTML iconHTML  

    We propose an innovative thermal modeling approach that takes into account different “levels-of-knowledge” as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity. View full abstract»

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  • Electronics cooling by extended surface: Refractive index changes flow visualization of the natural convection heat transfer

    Page(s): 39 - 45
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    Natural convection heat transfer occurs when the fluid buoyancy motion is induced by density differences themselves caused by the heating. A temperature gradient causes a density variation in a cooling fluid with a related local change in the refractive index. The gradient of refractive index has the effect of bending the light. The thermal load of the device causes an optical deflection in the cooling fluid that an opportune light probe can reveal. Analyzing the deflection of the light probe it is possible to go back to the related temperature gradient. The experimental work in this paper represents a very simple method for the visualization of refractive index non homogeneities in a phase object: the temperature gradients in a cooling fluid for buoyancy-induced convective flow can be visualized in an electronic system during its operation. The developed experimental set-up allows to reveal local refractive index changes in a phase objects. A fringe pattern is acquired, through the cooling fluid under analysis, with a digital camera two times: the first one with the fluid at rest, the second one with the thermal load due to the electronic device normal operation. By the means of the MATLAB processing of the acquired images it's possible to reveal the shape and the directions of the thermal flow lines for the cooling fluid. In this way we can obtain a deeper understanding of the optimal convection working volume or information for the optimization of the relative spatial positioning of the several electronic components in a complex electronic system, like a printed circuit board (PCB). The experimental set-up was optically implemented: the analysis is absolutely no-contact and carried out without distortion for the thermal flow and without alteration for the temperature gradients in the fluid under test. The proposed technique has been applied on two typical heat extraction situations recurrent in the electronic devices: are presented the experimental results of t- e visualization of the natural convection buoyancy driven air flow for an heat sink and a power resistor. In both the cases it was possible to visualize the bouyancy induced flow generated, in air, by the heated sample and understand the shape of the isogradients lines in the test field and the involved working volume in the cooling fluid. The results presented show that is possible to monitore the onset and the development of the natural convection thermal flow and the perturbation in the thermal gradient map caused by externally added air flow with a simple and cheap noninvasive optical setup. View full abstract»

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  • Empirical feasibility assessment of energy scavenging opportunity in compact mobile computers

    Page(s): 331 - 334
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    The opportunity of thermoelectric energy scavenging from waste heat of a compact and thermally limited notebook computer is experimentally studied in this paper. Thermal characterization of the target computer is done under a range of workloads/activity levels. A detailed finite element model of the system is developed for thermal simulations and the results are validated by the ones obtained in the thermal characterization. A suitable spot is selected based on the finite element model for integration of thermoelectric module into the cooling solution without impacting the system performance, as measured by thermal changes in the simulation model. A significant difference of approximately 22 °C is observed between the hot and cold side of thermoelectric module when the system is executed at maximum workload resulting in a net power generation of 410.5 μW. The generated power scales down to 60.5 μW when the system is idle. It has been verified through lab experiments that the integration of thermoelectric module to a thermally limited notebook system can be done without any substantial degradation in performance. View full abstract»

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  • Experimental investigation of uninterrupted and interrupted microchannel heat sinks

    Page(s): 147 - 150
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    In this work, the relation between heat transfer performance and interruption of microchannels was investigated. Experiments were conducted on uninterrupted and interrupted aluminium channel heat sinks of different channel widths. Two different types of interrupted channels were tested: channels having single interruption and 7 interruptions. Distilled water was used to remove a constant heat load of 40 W in the volumetric flow rate range of 0.5-1.1 lpm. The interruption of channels improved the thermal performance over the uninterrupted counterparts up to 20 % in average Nusselt number, for 600 micron-wide channels. The improvement of average Nusselt number between the single interrupted and multi interrupted channels reached a maximum value of 56 % for 500 micron-wide channels. This improvement did not cause a high pressure drop penalty. In the tests, maximum temperature difference between the inlet of the fluid and the base of the channel was observed as 32.8°C. View full abstract»

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  • Fabrication and characterization of a metal matrix polymer fibre composite for thermal interface material applications

    Page(s): 286 - 292
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    Dealing with increasing power densities in high performance micro- and power -electronics applications is continuously becoming more challenging. Many applications today need thermal interface materials (TIMs) that can offer significantly higher performance than what is currently available. One of the main challenges for TIMs is to combine material properties that result in the thermo-mechanical characteristics required. Solder TIMs can provide excellent thermal transport, but high stiffness, causing lack of sufficient thermal-mechanical decoupling, limits their applicability. To mitigate these issues we pursue the development of a composite metal matrix based TIM technology concept with potential to combine high thermal conductivity with low joint stiffness. In this work we optimize the fabrication of an indium matrix polyimide fibre composite and investigate its thermal performance as an interface material. The fabricated composite is shown to have high effective thermal conductivity (up to 22 W/mK) and result in low contact resistance (<;1 Kmm<;sup>2<;/sup>/W). View full abstract»

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  • Failure prediction of IGBT modules based on power cycling tests

    Page(s): 270 - 273
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    This article describes a possible method to assess the long-time behaviour of IGBT modules using the combination of power cycles to stress the devices and thermal transient testing to monitor possible die-attach degradation. The failure of an IGBT module is a complex phenomenon; it consists of thermal, electrical and thermo-mechanical effects. After a theoretical overview of the possible mechanisms, a detailed description on the structure of selected IGBT module and the power cycling parameters is given. To better understand the temperature distribution on the device and the reason of the failure after the cycling, the module was opened up, inspected visually and an equivalent thermal model was built and calibrated to the physical test results. Failure mechanisms such as die attach resistance increase, wire bond cracking and gate oxide degradation were detected. View full abstract»

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  • Free standing thermal interface material based on vertical arrays composites

    Page(s): 244 - 247
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    In power microelectronics, the trends towards miniaturization and higher performances result in higher power densities and more heat to be dissipated. For large systems, the associated thermal architecture is becoming more and more complex and costly. In most electronic assembly, thermal interface materials (TIM) help provide a path for the heat to be transferred from the hot source to a cooler heat sink but still represent a bottleneck in the total thermal resistance of the system. Increasing the dissipative capabilities of thermal interface materials is a widely tackled challenge. For this study we address more specifically the “gap filler” type of TIM. Typically located beneath packaged dies, it features height compensation capabilities, CTE mismatch handling, easy replacement and high thermal conductivity. We report here on the fabrication of a composite free standing film based on vertically aligned carbon nanotubes. Original processing methods are reported as well as first applicability assessments as thermal interface material. View full abstract»

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  • Fully-coupled 3D electro-thermal field simulator for chip-level analysis of power devices

    Page(s): 210 - 215
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    The paper presents a novel approach to modelling static and dynamic electro-thermal effects in large integrated and discrete semiconductor power devices. Electrical and thermal equations are solved simultaneously and selfconsistently from a single set of equations. A high spatial resolution allows accurate modelling of metal layers as required for advanced integrated BCD technologies. The simulator uses a well-adapted mesh for the substrate, which is important for the simulation of the temperature. Thus, both the voltage drop in the on-chip metallization as well as the device temperatures can accurately be determined without sacrificing accuracy or limiting the applicability of the simulator to special cases. Electrical and thermal conductivities of both metal and substrate are temperature dependent. Measurement and simulation results for test chips and real DMOS driver stages with small integrated temperature sensors are presented. An excellent match is observed even for very high temperatures exceeding 300°C. The tool integrates easily in an industrial design environment with direct import of GDS layout and ITF technology data. View full abstract»

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  • Generation of electro-thermal models of integrated power electronics modules using a novel synthesis technique

    Page(s): 216 - 221
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    In recent years, the development of electronic systems that make use of high-rate power circuitry is increasingly frequent also for markets going beyond the typical industrial sector. So, the implementation of efficient electronic modules aimed at converting power, in ambits such as renewable energy equipment or hybrid-electric vehicle motor drives, represents a new challenge for designers. Often, the amount of power to be managed is very significant and no rarely it exceeds tens of kW. In this context, new concepts for manufacturing power converters are emerging and Integrated Power Electronics Modules (IPEM) represent a solution which guarantees better performances. The design of applications exploiting IPEM concept requires multi-domains simulation models able to predict the thermal behaviour of the module according to its electrical performances. In this work, a new methodology aimed at automatizing the synthesis of PSpice-like models able to reproduce both electrical and thermal dynamics is discussed. The model, generated by starting with a series of data retrieved by FEM simulations, exploits a mapping between electrical and thermal quantities and allows reproducing the characteristics of the module in a pure PSpice simulation environment. After a description of the electro-thermal model and the related developed EDA synthesis environment, a series of simulation issues are discussed. View full abstract»

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  • Heat flux sensor for power loss measurements of switching devices

    Page(s): 327 - 330
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    The measurement of the power dissipated by a semiconductor device is of great importance for assessing system performance and reliability and to evaluate the overall efficiency of a power electronics systems. Efficiency measurement can be difficult when the device is highly efficient and the power losses are extremely low. Measurement errors can be introduced due to high frequency components in the waveforms. We present a calorimetric method based on a micromachined dual-sensor heat-flux measurement device that allows the estimation of the power dissipated by a semiconductor device. The system use a thermoelectric heat pump to keep the switching device at room temperature in order to minimise the heat exchanged with the ambient and improve therefore the precision of the measurement. View full abstract»

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  • Hybrid porous media and fluid domain modeling strategy to optimize a novel staggered fin heat sink design

    Page(s): 224 - 230
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    In this paper, we propose a novel lid-integrated cold plate with distributed fluid delivery architecture to a silicon microchannel heat exchanger. The microchannels consist of a staggered fin array. The manifold topology tolerates the use of a one-component lid, compatible with high volume fabrication processes, such as injection molding. A multi-scale modelling methodology based on the porous media approximation is introduced and compared with experimental results. The fluid cavity of the heat exchanger in the full heat sink model is represented as a two-dimensional porous domain. This approximation reduces the computational cost to solve the conjugate heat and mass transfer problem significantly. The characteristic of the cold plate is discussed based onfull heat sink model results. The main pressure drop of 93%for the base-line case can be attributed to the losses in the staggered fin array. The flow non-uniformity in the heat exchanger is less than 1.2% A sensitivity analysis with the objective o.f reducing the pumping power for a nominal thermal performance was performed based on a lumped model. it is preferable to increase the number of sub-sections and to reduce the fin dimension in the heat exchanger. The increase in access slit width is of moderate importance. The optimal case computed has 100 pm wide microchannelfins, accessed by 8 manifold.fingers that have 400 pm wide slits at their bottom. This case requires 0.5 W pumping power for a thermal resistance of 12 Kmm2/W. View full abstract»

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