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Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on

Date 22-22 Oct. 1999

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  • 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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    Freely Available from IEEE
  • Author index

    Page(s): 751 - 753
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    Freely Available from IEEE
  • A co-design based high-performance real-time GIS

    Page(s): 410 - 419
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    This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility View full abstract»

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  • Energy issues in multimedia systems

    Page(s): 24 - 33
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    This paper presents possible optimization to reduce the energy budget for systems-on-chip (SoC) designs that will be used in next generation multimedia systems. Since future multimedia systems will include the processor core(s), the entire memory system, system buses, I/O controllers, system clocking and control and, in wireless applications, RF components, all on one chip, lowering power dissipation in next generation multimedia chips presents a number of design challenges. Possible strategies for managing the power budget in future multimedia SoCs are presented. Reducing the power consumption of the memory system, system control, and system buses are a particular focus View full abstract»

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  • Symmetric and programmable multi-chip module for rapid prototyping system

    Page(s): 301 - 310
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    To accelerate prototyping designs, we propose a new Symmetric and Programmable MCM (SPMCM) substrate, which consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Especially, the FPIC that we developed contains two kinds of polygonal routing modules and some virtual-wires to reduce the number of routing switches and pin count. For a bare-chip slot with 2n pads, the number of switches used in the polygonal routing module is less than the conventional routing module by √(rFCn)/4 times, where the flexibility ratio r(FC) is close to 1 View full abstract»

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  • A detailed analysis of MediaBench

    Page(s): 448 - 455
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    In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. MediaBench performance characteristics were examined by running MediaBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch prediction accuracy, cache hit rates, memory usage, and integer bit utilization were considered. This information can be of use in designing embedded systems targeted at multimedia applications View full abstract»

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  • Configuration-based architecture for high speed and general-purpose protocol processing

    Page(s): 540 - 547
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    A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications View full abstract»

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  • NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform

    Page(s): 159 - 168
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    Conventional Distributed Arithmetic (DA) is popular in ASIC design and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in Digital Signal Processing (DSP) applications. Mathematical analysis proves that NEDA can implement inner product of vectors in the form of 2's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative study shows that NEDA outperforms widely-used approaches such as MAC and DA in many aspects. Being a high speed architecture free of ROM, multiplication and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architecture for one dimensional DCT core is presented as an example View full abstract»

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  • Efficient dataflow representation of MPEG-1 audio (layer III) decoder algorithm with controlled global states

    Page(s): 341 - 350
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    We present an efficient dataflow representation of MPEG-1 Audio (Layer III) Decoder (MP3) algorithm with controlled global states. Although dataflow graph has been a successful representation language for DSP applications, lack of global states makes it unsuitable to some applications that require periodic parameter update and dynamic behavior of function blocks. We show the global states can solve these problems and be fused into dataflow graph without any side effect. With a real-life example such as MP3 decoder, we present the novelty and usefulness of our approach View full abstract»

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  • 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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    The following topics were dealt with: block matching architectures; video architectures; heterogeneous and reconfigurable DSPs; DSP architectures and design methodology; next generation multimedia architecture and algorithms; audio decoding; multimedia and image processing; wireless applications; communication and encryption; acoustic signal processing; architectures for FFT; and DSP algorithms and arithmetics View full abstract»

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  • An implementation of MPEG-2 transport stream multiplexer

    Page(s): 379 - 389
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    In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper View full abstract»

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  • Source localization and spatial filtering using wideband MUSIC and maximum power beamforming for multimedia applications

    Page(s): 625 - 634
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    We propose a 2-D beamforming system that is designed for multiple source localization, signal enhancement, interference suppression, and noise reduction. The 2-D locations of the sources can be estimated by the wideband MUSIC algorithm. After estimating the locations of the sources, the maximum power beamforming algorithm is applied to enhance the desired signal and attenuate undesired spatially distributed interferences and background noises. Performance gains from simulations and experiments are shown to be promising for multimedia applications View full abstract»

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  • Low power strategy about correlator array for CDMA baseband processor

    Page(s): 513 - 522
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    This paper discusses the design, implementation, and performance evaluation of a low powered correlator architecture for multi-code CDMA systems. In CDMA systems, correlators are used to de-spread the received signals and are important blocks for RAKE receivers. We proposed a low powered correlator architecture to de-spread input with several PN sequence concurrently, According to our preliminary simulation results, the suggested architecture can de-spread the input signal with two PN codes simultaneously and save 41% power consumption compared with traditional correlator architecture View full abstract»

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  • Analysis of the intrinsic transient fault tolerance of a signal and image processing algorithm implemented on a DSP

    Page(s): 462 - 471
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    We present in this article a method to analyse the intrinsic transient fault tolerance of signal and image processing algorithms for DSP applications. This method allows to protect only non-tolerant parts and consequently to decrease time and memory overheads. Results are given for an algorithm of embedded satellite image compression View full abstract»

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  • Parametrizable behavioral IP module for a data-localized low-power FFT

    Page(s): 635 - 644
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    FFTs are important modules in embedded telecom systems, many of which require low-power real-time implementations. This paper describes a technique for aggressively localizing data accesses in a (inverse) fast Fourier transformation at the source code level. The global I/O functionality is not modified and neither is the bit-true arithmetic behavior. Typically 20 to 50% of the background memory accesses can be saved. A heavily parametrizable solution is proposed which leads to a family of power optimized algorithm codes. Moreover, efficient coding details for specific instances are shown View full abstract»

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  • Energy-scalable protocols for battery-operated microsensor networks

    Page(s): 483 - 492
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    To maximize battery lifetimes of distributed wireless sensors, network protocols and data fusion algorithms should be designed with low power techniques. Network protocols minimize energy by using localized communication and control and by exploiting computation/communication tradeoffs. In addition, data fusion algorithms such as beamforming aggregate data from multiple sources to reduce data redundancy and enhance signal-to-noise ratios, thus further reducing the required communications. We have developed a sensor network system that uses a localized clustering protocol and beamforming data fusion to enable energy-efficient collaboration. We have implemented two beamforming algorithms, the Maximum Power and the Least Mean Squares (LMS) beamforming algorithms, on the StrongARM (SA-1100) processor. Results from our experiments show that the LMS algorithm requires less than one-fifth the energy required by the Maximum Power beamforming algorithm with only a 3 dB loss in performance. The energy requirements of the LMS algorithm was further reduced through the use of variable-length filters, a variable voltage supply, and variable adaptation time View full abstract»

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  • A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

    Page(s): 558 - 567
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    In this paper, a novel VLSI design for an all digital QAM channel equalizer is presented. We adopted a decision-feedback equalizer (DFE) structure to combat the inter-symbol-interference (ISI) induced during high speed data communication. The equalizer consists mainly of eight transversal adaptive filters and slicers. Since the adaptive filter along with the slicer will form a nonlinear feedback path, the resultant recursive computing often leads to a severe performance bottleneck. To overcome this, a bit serial, MSB first computing scheme based on distributed arithmetic and signed digit number system techniques was developed. In our scheme, the next symbol's equalization can be started as soon as the MSD of the current symbol is obtained. This leads to a computation overlap between successive symbol's equalization and can effectively improve the baud rate. The circuit complexity, however, is still kept low with the help of fine grain pipelining. With careful arrangement of data flow, an efficient systolic array design with 100% utilization and suitable for VLSI implementation is derived. The design architecture is also scalable in that the initiation interval between the processing of two consecutive symbols is a constant of 5+[m/4] clocks (in the delayed sign LMS case) and the hardware complexity is of order 2·m·(n+1), where m and n are tap order and word length View full abstract»

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  • An improved pyramid algorithm for synthesizing 2-D discrete wavelet transforms

    Page(s): 75 - 80
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    The pyramid algorithm (PA) has been shown very suitable for computing 2-D forward and inverse discrete wavelet transforms (DWT). In this paper, we present a new 2-D synthesis PA to improve some defects encountered in the classical PA algorithm that usually requires large latency, long computation time, and big memory space. Unlike the PA algorithm which computes a 2-D IDWT level by level, our proposed algorithm performs a 2-D DWT in word size. Thus, for processing an N×N 2-D IDWT with m levels and L-tap filters, the proposed algorithm needs a latency of 3m+4, computes only in N2 clock cycles, and spends 2NL+4(m-1) memory space View full abstract»

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  • Design of threshold Boolean filters under MSE criterion by iterative searching

    Page(s): 663 - 670
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    Threshold Boolean filters (TBFs) constitute a large class of nonlinear filters which are effective in removing impulsive noise and preserving image details. The minimum mean square error (MMSE) design of TBFs is found to be a quadratic 0-1 programming problem. Unfortunately, solving the problem needs a huge number of computations. We propose an iterative search algorithm of very low complexity to solve the design problem sub-optimally. In each iteration, only one variable is considered and updated. Simulation shows that the proposed algorithm converges quickly and often converges to the optimal solution View full abstract»

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  • A low-power multimedia communication system for indoor wireless applications

    Page(s): 473 - 482
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    A low-power multimedia communication system is proposed. Power reductions are achieved by employing dynamic algorithm transforms and joint source-channel coding to reconfigure the system in the presence of variabilities in source and channel data. Configuration parameters are source rate, error correction capability of the channel encoder/decoder, number of powered-up fingers in the RAKE receiver and transmit power of the power amplifier. Energy-optimum configurations are obtained by minimizing energy consumption under the constraints of end-to-end distortion and total transmission rate. The proposed system is tested over a variety of images, distances (ranging from 2 to 100 meters) and multipath channels. Simulation results using 0.18 μm, 2.5 V CMOS parameters show that the reconfigurable system can achieve average energy savings of 59% as compared to a fixed system designed for the worst case. Also, the proposed system consumes 16% less energy as compared to a transmit-power-controlled system View full abstract»

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  • A Gabor filter-based approach to fingerprint recognition

    Page(s): 371 - 378
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    We propose a Gabor-filter-based method for fingerprint recognition in this paper. The method makes use of Gabor filtering technologies and need only to do the core point detection before the feature extraction process without any other pre-processing steps such as smoothing, binarization, thinning, and minutiae detection. The proposed Gabor-filter-based features play a central role in the processes of fingerprint recognition, including local ridge orientation, core point detection, and feature extraction. Experimental results show that the recognition rate of the k-nearest neighbor classifier using the proposed features is 97.2% for a small-scale fingerprint database, and thus that the proposed method is an efficient and reliable approach View full abstract»

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  • Performance evaluation of motion estimation algorithms for digital signal processors

    Page(s): 35 - 43
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    Current implementations of MPEG2 encoders are specially designed in order to perform a huge number of operations, most of which occur during motion estimation. Many fast algorithms have been proposed to reduce the processing power necessary. This paper examines the results achieved by several methods that show promise for reducing computation while sacrificing as little image quality as possible. Methods that achieve these goals are desirable for use in future encoders that will be implemented on generic digital signal processors (DSPs) View full abstract»

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  • Real-time software video codec with a fast adaptive motion vector search

    Page(s): 44 - 53
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    A PC-based real-time software MPEG-4 video codec with a fast adaptive motion vector search is presented. In a fast adaptive motion estimation (ME) technique, the search order is dynamically changed in accordance with the motion of objects. This technique suppresses load fluctuation in the ME and contributes to the stable real-time work of the codec. MMX instructions are used to increase the codec speed. On a portable PC, the software video codec supports satisfactory mobile visual communication at 64 kbps and 128 kbps, for example, at QCIF 15 fps. The codec on a 450 MHz Pentium II processor can encode and decode 30 CIF frames in real-time View full abstract»

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  • A novel hardware algorithm for residue evaluation

    Page(s): 671 - 680
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    An efficient hardware algorithm for the conversion of an integer X to its residue module a predefined integer m, is introduced. The algorithm is based on successive subtractions of appropriately selected multiples of m, from the input X, and it leads to fast evaluation of the residue, via hardware of low complexity. A VLSI architecture for the implementation of the algorithm is also proposed View full abstract»

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  • Power reduction in wireless receivers through multistage digital filtering and quantization

    Page(s): 523 - 531
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    The number of bits required to accurately represent a received signal in a wireless system changes as the out-of-band interference is removed by an IIR digital filter, if the filtering is done in stages, such as second-order sections. Taking advantage of this fact can reduce the size of the datapath in a VLSI realization of a digital filter, and hence power and area can be saved without decreasing performance. An effective algorithm for computing this reduced number of bits to use for quantization after each stage is derived, and a scheme for optimally ordering the second-order sections is presented, power savings range from 33% to 50%, depending on the amount of out-of-band interference View full abstract»

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