Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Date 22-22 Oct. 1999
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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
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PDF (271 KB)
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Author index
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PDF (93 KB)
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VLSI architecture for very high resolution scalable video coding using the virtual zerotree
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PDF (408 KB)
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A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors
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PDF (500 KB)
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Architecture and implementation of a single-chip programmable digital television and media processor
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PDF (460 KB)
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Enhanced DSP core for embedded applications
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PDF (532 KB)
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Efficient dataflow representation of MPEG-1 audio (layer III) decoder algorithm with controlled global states
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PDF (656 KB)
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Design and implementation of an adaptive FIR filter based on delayed error LMS algorithm
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PDF (240 KB)
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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
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PDF (24 KB)
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NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform
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PDF (376 KB)
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Digital watermarking through quasi m-arrays
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PDF (172 KB)
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Source localization and spatial filtering using wideband MUSIC and maximum power beamforming for multimedia applications
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PDF (548 KB)
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Principle and applications of asymmetric crosstalk-resistant adaptive noise canceller
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PDF (376 KB)
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Configuration code generation and optimizations for heterogeneous reconfigurable DSPs
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PDF (616 KB)
