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VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on

Date 5-7 Aug. 2013

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Displaying Results 1 - 25 of 60
  • Additional reviewers

    Page(s): viii - ix
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  • Author index

    Page(s): 1 - 5
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  • [Copyright notice]

    Page(s): 1
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    Freely Available from IEEE
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • Proceedings 2013 IEEE Computer Society Annual Symposium on VLSI [sponsors and organizers]

    Page(s): 1
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    Freely Available from IEEE
  • Embedded systems design for smart system integration

    Page(s): 32 - 33
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    Summary form only given. Smart or intelligent system is a new technology term that will be found in many applications in our daily life and industries in the future for examples in energy management, medical applications and healthcare management, industrial automation and automotive. Based on its technological term, smart systems should have capabilities to solve very complex problems, including taking over human cognitive functions. Due to the exponential increase of world energy demand, in which between 2010 and 2030 is estimated to be 45%, energy management will be one of the most urgent topics of the century and a significant driver for the evolution of semiconductors and electronics products. The important issues in the energy management are efficiency and reliability. Those requirements initiate the movement of power technology trend from traditional into smart grids concept. Cybersecurity and control systems for instance will be important topics for future smart grid systems. In medical applications and healthcare management, smart products are mainly dedicated to improve the quality of health treatments and rehabilitations. The key components of the products are sensors (biomedical sensors). They should be miniaturized, which is enabled by using Micro-Electro-Mechanical System (MEMS) technology, in order to minimize the physical effect on the biologic system. The key factor of the smart systems is new inventions in the fields of nanotechnology, advanced materials, biotechnology, photonic technology and nanoelectronics. The innovation of efficient computing algorithms should be a challenging issue to implement the nanoelectronic products. The integration of the nanoelectronic products into smart systems should consider both arts and cost aspect. Therefore, the miniaturization of smart products, which is affected by efficient computing algorithms and nano-scale technologies, will be an interesting feature for end-users on market. View full abstract»

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  • HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications

    Page(s): 145 - 146
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    Summary form only given. The recent spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a very complex multi-processor system on a single chip (MPSoC), mobile and autonomous computing, global networking and wire-less communication, and facilitated a fast progress in these areas. New important opportunities have been created. The traditional applications can be served much better and numerous new sorts of embedded systems became technologically feasible and economically justified. Various monitoring, control, communication or multi-media systems that can be put on or embedded in (mobile, poorly accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern embedded application impose very stringent functional and parametric demands. Moreover, the spectacular advances in microelectronics introduced unusual silicon and system complexity. The combination of the huge complexity with the stringent application requirements results in numerous serious design and development challenges, such as: accounting in design for more aspects and related complex multi-objective MPSoC optimization, adequate resolution of numerous complex design tradeoffs, reduction of the design productivity gap for the increasingly complex and sophisticated systems, reduction of the time-to market and development costs without compromising the system quality, etc. These challenges cannot be well addressed without an adequate system and design methodology adaptation. The first part of the presentation is devoted to discussion of the serious issues and challenges in development of contemporary and future demanding embedded systems and introduction of the quality-driven model-based design methodology proposed by the presenter. Subsequently, the Intel's ASIP-based MPSoC technology is introduced, and a new automatic design flow for heterogeneous ASIP- based MPSoCs- is discussed, when focusing on the system and processor level design- space exploration (DSE) involving coherent HW/SW architecture co-synthesis, macro- and micro-architecture design tradeoff exploitation, and application-specific memory and communication design. This flow and its EDA tools are results from the European research project ASAM (Automatic Architecture Synthesis and Application Mapping for MPSoCs based on adaptable ASIPs) performed in the framework of the industrial research program ARTEMIS. The final presentation part overviews several methods and EDA-tools of the ASAM flow focusing on the micro-architecture level DSE involving the application analysis and parallelization, ASIP micro-architecture synthesis and application scheduling and mapping, combined in one coherent HW/SW co-synthesis process. View full abstract»

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  • Recent advances and challenges in physical design automation

    Page(s): 223
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    Summary form only given. A key factor that enabled the development of the microelectronics industry was the creation of sophisticated software tools for design automation. The tremendous evolution of manufacturing capacity was primarily fuelled by scaling down the transistors. Thus, besides being possible to integrate an increasing number of devices, they have also become increasingly faster. However, this wonderful manufacturing capacity would be of little use if it were not possible for human designers to specify the different functions, structures and physical characteristics of highly complex projects in a progressively more efficient way. That is why the most traditional design problems such as placement, routing, gate sizing, are still hot topics today. In the last years, all these subjects regained a lot of attention and experimented significant, sometimes radical, advancements. In this talk we review basic concepts at the definition of such problems, which in general require combinatory optimization, and cover some of the most important achievements in placement and routing in the last decade. They were made possible by the combined effort of industry and academia with the release of realistic benchmark sets and the promotion of several research contests. Finally, we can better understand some of the current challenges that must be faced to keep pace with the next big designs, highlighting the relevance of research in this area. View full abstract»

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  • Do we need wide flits in Networks-on-Chip?

    Page(s): 2 - 7
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    Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system. View full abstract»

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  • Determining the test sources/sinks for NoC TAMs

    Page(s): 8 - 13
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    Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in shorter tests. The contribution of this paper is to present the part of the test flow which determines the optimal number and location of the test sources and sinks in a NoC TAM without constraining the test scheduler. Searching the minimal number of sources/sinks can minimize the silicon area overhead since each NoC source/sink requires about 4300 gates for a NoC channel with 32-bit width. View full abstract»

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  • Real-time low-power task mapping in Networks-on-Chip

    Page(s): 14 - 19
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    Many state-of-the-art approaches to power minimisation in Networks-on-Chip (NoC) are based on the reduction of the communication paths taken by packets over the interconnect. This is often done by optimising the packet routing, the allocation of tasks that produce and consume those packets, or both. In all cases, the optimisation affects the timeliness of the packets, because changes will occur in the way resources are shared at the platform cores (as tasks are reallocated) and NoC links (as packet routes are changed). In this paper, we propose an optimisation technique that is able to minimise power dissipation without sacrificing timing constraints, thus suitable to systems with hard real-time requirements. It is based on a Genetic Algorithm (GA) that evolves chromosomes representing the mapping of tasks to cores, guided by a multi-objective fitness function that combines power estimation macromodels and real-time schedulability analysis. View full abstract»

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  • Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designs

    Page(s): 20 - 25
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    Functional verification of data dominated high-level designs is a major concern in modern integrated circuit production flow. On the one hand, the size and complexity of the input state-space prevent conventional validation strategies to check the behaviour of the design thoroughly using simulation. On the other hand, formal verification methods still face difficulties while verifying high-level designs, specially when complex data types and dynamically allocated data structures are used. This work presents a method based on guiding heuristics for dynamically checking temporal properties of high-level designs. The properties are translated into heuristic functions that are combined with the black-box model of the system in order to guide the validation effort to error prone regions of the design's input domain. The functions are designed in a way that their minimum points correspond to properties violations, if they exist. Optimization algorithms are used to evaluate the property under check by searching for input sequences that minimize the heuristic functions. Experiments indicate a significant improvement in the efficiency of the verification process when the proposed method is used, with respect to both random simulation and bounded model checking. View full abstract»

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  • Data extraction from SystemC designs using debug symbols and the SystemC API

    Page(s): 26 - 31
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    Due to the ever increasing complexity of hardware and hardware/software co-designs, developers strive for higher levels of abstractions in the early stages of the design flow. To address these demands, design at the Electronic System Level (ESL) has been introduced. SystemC currently is the “defacto standard” for ESL design. The extraction of data from system designs written in SystemC is thereby crucial e.g. for the proper understanding of a given system. However, no satisfactory support of reflection/introspection of SystemC has been provided yet. Previously proposed methods for this purpose either focus on static aspects only, restrict the language means of SystemC, or rely on modifications of the compiler and/or parser. In this work, we present an approach that overcomes these limitations. A methodology is introduced which enables full extraction of the desired information from a given SystemC design without changing the SystemC library or the compiler. For this purpose, debug symbols generated by the compiler and SystemC API calls are exploited. The proposed system retrieves both, static and dynamic information. A comparison to previously proposed solutions shows the benefits of the proposed method, while its application is illustrated by means of a visualization engine. View full abstract»

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  • LImbiC: An adaptable architecture description language model for developing an application-specific image processor

    Page(s): 34 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (810 KB) |  | HTML iconHTML  

    Due to their ease of integration and widespread adoption, General Purpose Processors (GPP) are presently used in a wide range of applications. However, the highly flexible nature of a GPP leads to overhead in terms of power, performance and area for a specific application. Another approach, proposed by this paper, is to use Application-Specific Instruction-set Processors (ASIP) that are specifically adapted to a given application. To decrease development time and effort and consequently time-to-market, a model-based development process is used. The high-level model allows for automated generation of software development tools, simulation models and RTL models from a single source. An adaptable LISA model representing a simplified ARM Cortex-M1 processor is used as a base, which is then supplemented by application-specific features requested by the software developer or system architect. This paper presents a working example of this concept, in which a state-of-the-art processor model, we call LImbiC, is extended to meet the requirements of a specific application. Specifically, custom instructions are added to the LImbiC processor to improve its performance in the particular task of image processing. In addition, during the development process infrequently used or obsoleted instructions can be removed, which allows for separate versions of LImbiC to meet varying design goals within the design space exploration. View full abstract»

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  • A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context

    Page(s): 40 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    The emergence of many wireless standards is introducing the need of flexible multi-standard baseband receivers. To address this issue and to face the increasing demand of higher throughput for new greedy applications on mobile devices recent works propose multi-ASIP platforms for decoding algorithms. Furthermore dynamic evolution of communication parameters combined with the reduction of latency between two data frames imposes the need for an efficient reconfiguration management of such systems. In this context, we propose to tackle reconfiguration optimizations of a multi-standard and multi-mode ASIP for turbo decoding in order to improve the global reconfiguration management of a multi-ASIP platform. A comprehensive analysis concerning the area impact and dynamic reconfiguration performance is presented. Proposed ASIP configuration optimizations lead to a low area overhead of 0.004 mm2 in 65 nm CMOS technology. For a multi-ASIP platform in which 8 ASIPs are implemented on a same device the configuration load is divided by ten thanks to both ASIP optimizations and an efficient configuration infrastructure. View full abstract»

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  • A study on polymorphing superscalar processor dynamically to improve power efficiency

    Page(s): 46 - 51
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    Asymmetric Multicore Processors (AMP) have emerged as likely candidates to solve the performance/power conundrum in the current generation of processors. Most recent work in this area evaluate such multicores by considering large (usually out-of-order (OOO)) and small (usually in-order (InO)) cores on the same chip. Dynamic online swapping of threads between these cores is then facilitated whenever deemed beneficial. However, if threads are swapped too often, the overheads may negatively impact the benefits of swapping. Hence, in most recent work, thread swapping decisions are made at coarse grain instruction granularities, leaving out many opportunities. In this paper, we propose a scheme to mitigate the penalty imposed by thread swapping and yet achieve all the benefits of AMPs. Here, a single superscalar OOO core morphs itself into an InO core at runtime, whenever determined to be performance/Watt efficient. Certain Intel processors already have a similar mechanism to statically morph an OOO core to an InO core to facilitate debug. We extend this existing capability to perform dynamic core morphing at runtime with an orthogonal objective of improving power efficiency. Results indicate that on an average, performance/Watt benefits of 10% can be extracted by our proposed morphing scheme at a very small performance penalty of 3.8%. Since this scheme is based on existing mechanisms readily available in current microprocessors, it incurs no hardware overheads. View full abstract»

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  • Ground gated 8T SRAM cells with enhanced read and hold data stability

    Page(s): 52 - 57
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    A new asymmetrically ground-gated eight-transistor (8T) static random access memory (SRAM) circuit with enhanced data stability characteristics is proposed in this paper. A robust and low leakage SLEEP mode with data retention capability is provided by utilizing asymmetrical ground gating in an idle memory array. The data stability is enhanced by 2.22× and 53.54% during read operations and data retention SLEEP mode, respectively, with the proposed asymmetrically ground-gated 8T memory circuit as compared to a conventional ground-gated six-transistor (6T) SRAM cell in a TSMC 65nm CMOS technology. The overall electrical quality is also enhanced by 2.84× with the proposed asymmetrically ground-gated 8T SRAM circuit as compared to the conventional ground-gated 6T memory array. View full abstract»

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  • A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions

    Page(s): 58 - 63
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    This paper discusses, for the first time, how the statistical SRAM design analyses should be changed when: (1) the shift-amount of the time-dependent (TD) voltage margin variations (MV) after the screening test will become larger than that before and (2) the shapes of the MV distribution will change from the Gaussian to the complex mixtures of Gamma distributions. We discuss on the SRAM TD-MV analyses with not only the forward problem but also the inverse problem, i.e., deconvolution analyses. The proposed algorithm for the deconvolution to circumvent the issues caused by high-pass filtering behavior is discussed. Based on the proposed convolution /deconvolution design analyses, it has been shown for the first time that: (1) detecting the truncating point of the distributions of TD-MV by the screening test and (2) predicting the required the MV-shift-amount by the assisted circuit schemes to avoid the out of specs in the market during the life-time, etc, has become enabled based on the target specification. View full abstract»

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  • Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins

    Page(s): 64 - 69
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    A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42.7% shorter read delay, 36.9% lower write delay, and 75.4% wider voltage margin during write operations with the 7T SRAM cells while providing similar read static noise margin (RSNM) characteristics as compared to the conventional six transistor (6T) SRAM cells in TSMC 65nm standard CMOS technology. These performance benefits are achieved at the cost of 63.0% larger cell area, 70.6% higher read power consumption, and 57.9% higher write power consumption as compared to the conventional 6T SRAM cells. View full abstract»

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  • Dynamic encryption key design and management for memory data encryption in embedded systems

    Page(s): 70 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1031 KB) |  | HTML iconHTML  

    To effectively encrypt data memory contents of an embedded processor, multiple keys which are dynamically changed are necessary. However, the resources required to store and manage these keys on-chip (so that they are secure) can be extensive. This paper presents a design where each dynamic key is determined by a random number, a counter value, and a memory address, and is unique to the data in a memory location. The counter value, dedicated to a given memory location, controls the duration of the random number for the key associated with the location. The counter table and random number table are used for key storage. We reduce on-chip resources by customizing the counter table and allowing a pool of random numbers to be shared amongst the keys. The random numbers are dynamically updated during the application execution. We propose a key generation and management scheme such that the random number pool is extremely small (hence low memory consumption) yet sufficient for the uniqueness and randomness of each dynamic key. Experiments on a set of applications show that on average, large overhead (90% on chip area and 92% on power consumption) can be saved for a same security level, when compared to the state-of-the-art approach. View full abstract»

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  • A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES

    Page(s): 76 - 83
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    Advanced Encryption Standard (AES) is one of the most widely used cryptographic algorithms in embedded systems, and is deployed in smart cards, mobile phones and wireless applications. Researchers have found various techniques to attack the encrypted data or the secret key using Side Channel information (execution time, power variations, electro migration, sound, etc.). Power analysis attack is most prevalent out of all Side Channel Attacks (SCAs), the popular being the Differential Power Analysis (DPA). Balancing of signal transitions is one of the methods by which a countermeasure is implemented. Existing balancing solutions to counter power analysis attacks are either costly in terms of power and area or involve much complexity, hence lacks practicality. This paper for the first time proposes a double-width single core (earlier methods used two separate cores)processor algorithmic balancing to obfuscate power variations resulting in a DPA resistant system. The countermeasure only includes code/algorithmic modifications, hence can be easily deployed in any embedded system with a 16 bits bitwidth (or wider) processor. A DPA attack is demonstrated on the Double Width Single Core (DWSC) solution. The attack proved unsuccessful in finding the correct secret key. The instruction memory size overhead is only 16.6% while data memory increases by 15.8%. View full abstract»

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  • Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities

    Page(s): 84 - 89
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    This paper presents a fast and effective approach to cell-type selection and Vth assignment. In our approach, initially a solution without slew and load violation is generated. Then, the Lagrangian Relaxation considering lambda-delay sensitivities is used to reduce leakage power trying to keep the circuit without timing and load violations. If the set of cell-types given by Lagrangian Relaxation produces a circuit with negative slack, a timing recovery method is applied to find near-zero positive slack. The solution without negative slack is introduced to a power reduction step. The sizing produced using our approach could achieve up to 28% in power reduction compared to state of the art works. The leakage power of our solutions is, on average, 9.53% smaller than [1] and 12.45% smaller than [2]. Furthermore, the method is 19× faster than [1] and 1.18× faster than [2]. View full abstract»

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  • STAIRoute: Global routing using monotone staircase channels

    Page(s): 90 - 95
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    This work proposes a new algorithm for global routing using monotone staircase channels obtained from VLSI floorplan topology. Unlike the existing global routers that follow block placement stage, it immediately follows the floorplanning stage of VLSI design. The monotone staircase channels are identified using the results of recent O(nk log n) top-down hierarchical monotone staircase bipartition. The worst case time complexity of the proposed global routing algorithm is O(n2kt), where n, k and t denote the number of blocks, nets and the number of terminals in a given net respectively for a given floorplan. Experimental results on the MCNC/GSRC floorplanning benchmark circuits show that our method obtained 100% routability for each of the nets, without any over-congestion through the monotone staircase channels. The wire length for each of the t-terminal (t ≥ 2) nets is comparable to the steiner length of that net in almost all cases. View full abstract»

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  • A novel tool flow for increased routing configuration similarity in multi-mode circuits

    Page(s): 96 - 101
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    A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration (RTR) of an FPGA, all the modes can be time-multiplexed on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration of the reconfigurable region for every mode separately. This results in configurations that are bit-wise very different. Thus, in this case, many bits need to be changed in the configuration memory to switch between modes, leading to long reconfiguration times. In this paper we present a novel tool flow that retains the placement of the conventional RTR flow, but uses TRoute, a reconfiguration-aware connection router, to implement the connections of all modes simultaneously. DRoute stimulates the sharing of routing resources between connections of different modes. This results in a significant increase in the similarity between the routing configurations of the modes. In the experimental results it is shown that the number of routing configuration bits that needs to be rewritten is reduced with a factor between 2 and 4 compared to conventional techniques. View full abstract»

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  • On-chip clock error characterization for clock distribution system

    Page(s): 102 - 108
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    In this paper, we investigate a test strategy for characterization of clock error statistics between two clock domains in high-speed clocking systems (gigahertz and more). The method allows an indirect measurement (not based on time interval measurement) of clock error distribution by observing the integrity of a periodic sequence transmitted between two clocking domains. The method is compatible with fully on-chip implementation, and the readout of result to off-chip signals is cadenced at low rate. The strategy aims at picoseconds resolution without complex calibration. The idea was first validated by a discrete prototype at downscaled frequencies, and then a high frequency on-chip prototype was designed using 65 nm CMOS technology. Simulation results predict a measurement precision of less than ±2.5 ps. The article presents the theory, exposes the hardware implementation, and reports the experimental validation and simulation results of two prototypes. View full abstract»

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