2013 23rd International Conference on Field programmable Logic and Applications

2-4 Sept. 2013

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  • [Front cover]

    Publication Year: 2013, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2013, Page(s): i
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  • General chair message

    Publication Year: 2013, Page(s):ii - iv
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  • A note from the program chairs

    Publication Year: 2013, Page(s):v - vi
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  • Organizing committee

    Publication Year: 2013, Page(s):viii - x
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  • Steering committee

    Publication Year: 2013, Page(s): xi
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  • Program committee

    Publication Year: 2013, Page(s):xii - xvi
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  • External reviewers

    Publication Year: 2013, Page(s):xvii - xix
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  • Sponsors

    Publication Year: 2013, Page(s): xix
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  • Table of contents

    Publication Year: 2013, Page(s):xx - xxix
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  • Regular papers [breaker page]

    Publication Year: 2013, Page(s): 1
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  • Automated synthesis of FPGA-based heterogeneous interconnect topologies

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (335 KB) | HTML iconHTML

    The choice of the communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is a very large spectrum of interconnection topologies that potentially meet given communication requirements, determining various trade-offs between cost and performanc... View full abstract»

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  • Generating infrastructure for FPGA-accelerated applications

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (959 KB) | HTML iconHTML

    Whether for use as the final target or simply a rapid prototyping platform, programming systems containing FPGAs is challenging. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running on... View full abstract»

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  • The power of communication: Energy-efficient NOCS for FPGAS

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (465 KB) | HTML iconHTML

    Integrating networks-on-chip (NoCs) on FPGAs can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large “hard” blocks such as high-speed I/O interfaces. We propose mixed and hard NoCs that add less than 1% area to large FPGAs and run 5-6 x faster than the soft NoC eq... View full abstract»

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  • Altering LUT configuration for wear-out mitigation of FPGA-mapped designs

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (523 KB) | HTML iconHTML

    Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration o... View full abstract»

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  • Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (518 KB) | HTML iconHTML

    Soft-errors in LUT configuration bits of FPGAs can alter the functionality of an implemented design, rendering it useless, unless re-programmed. This paper proposes a technique to improve autonomous fault-masking capabilities of a design by maximizing the number of zeros or ones in LUTs. The technique utilizes spare resources (XOR gates and carry chain) of FPGA devices to selectively manipulate LU... View full abstract»

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  • Defect-robust FPGA architectures for intellectual property cores in system LSI

    Publication Year: 2013, Page(s):1 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (446 KB) | HTML iconHTML

    In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are re... View full abstract»

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  • Accelerating Random Forest training process using FPGA

    Publication Year: 2013, Page(s):1 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (164 KB) | HTML iconHTML

    Random Forest (RF) is one of the state-of-art supervised learning methods in Machine Learning and inherently consists of two steps: the training and the evaluation step. In applications where the system needs to be updated periodically, the training step becomes the bottleneck of the system, imposing hard constraints on its adaptability to a changing environment. In this work, a novel FPGA archite... View full abstract»

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  • FPGA-based K-means clustering using tree-based data structures

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (235 KB) | HTML iconHTML

    K-means clustering is a popular technique for partitioning a data set into subsets of similar features. Due to their simple control flow and inherent fine-grain parallelism, K-means algorithms are well suited for hardware implementations, such as on field programmable gate arrays (FPGAs), to accelerate the computationally intensive calculation. However, the available hardware resources in massivel... View full abstract»

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  • Accelerating maximum likelihood estimation for Hawkes point processes

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (222 KB) | HTML iconHTML

    Hawkes processes are point processes that can be used to build probabilistic models to describe and predict occurrence patterns of random events. They are widely used in high-frequency trading, seismic analysis and neuroscience. A critical numerical calculation in Hawkes process models is parameter estimation, which is used to fit a Hawkes process model to a data set. The parameter estimation prob... View full abstract»

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  • Titan: Enabling large and complex benchmarks in academic CAD

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (285 KB) | HTML iconHTML

    Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern designs which are large scale systems that make use of heterogeneous resources; however, most current FPGA benchmarks are both small and simple. In this paper we present Titan, a hybrid CAD flow that addresses these ... View full abstract»

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  • RIFFA 2.0: A reusable integration framework for FPGA accelerators

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (779 KB) | HTML iconHTML

    We present RIFFA 2.0, a reusable integration framework for FPGA accelerators. RIFFA 2.0 provides communication and synchronization for FPGA accelerated applications using simple interfaces for hardware and software. Our goal is to expand the use of FPGAs as an acceleration platform by releasing, as open source, a framework that easily integrates software running on commodity CPUs with FPGA cores. ... View full abstract»

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  • In pursuit of instant gratification for FPGA design

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (306 KB) | HTML iconHTML

    This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of precompiled modules and associated meta-data, bitstream-level assembly of desired designs can occur in a fraction of the time of traditional back-end tools. Modules are bound, placed, and routed using custom bitstream assembly with the primary ... View full abstract»

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  • A fully pipelined FPGA architecture for stochastic simulation of chemical systems

    Publication Year: 2013, Page(s):1 - 7
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (157 KB) | HTML iconHTML

    Simulation of chemical systems allows bio-chemists to understand how the interactions of individual molecules can lead to cellular and organism level behaviour. When the concentration of moleculesis very small, it is necessary to model every single chemical interaction in a Monte-Carlo simulation, presenting a huge computational burden. This paper presents a new fully pipelined architecture for ch... View full abstract»

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  • A hardware accelerated approach for imaging flow cytometry

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (907 KB) | HTML iconHTML

    Imaging flow cytometry uses high-speed flows and a camera to capture morphological features of hundreds to thousands of cells per second. These morphological features can be useful to isolate sub-populations of cells for life science research and diagnostics. Our experimental setup utilizes a high speed 208×32 resolution CMOS camera, operating at over 140,000 frames per second (FPS). In eac... View full abstract»

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