By Topic

2013 Euromicro Conference on Digital System Design

4-6 Sept. 2013

Filter Results

Displaying Results 1 - 25 of 149
  • [Front cover]

    Publication Year: 2013, Page(s): C4
    Request permission for commercial reuse | PDF file iconPDF (453 KB)
    Freely Available from IEEE
  • [Title page i]

    Publication Year: 2013, Page(s): i
    Request permission for commercial reuse | PDF file iconPDF (16 KB)
    Freely Available from IEEE
  • [Title page iii]

    Publication Year: 2013, Page(s): iii
    Request permission for commercial reuse | PDF file iconPDF (97 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2013, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (124 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2013, Page(s):v - xvii
    Request permission for commercial reuse | PDF file iconPDF (188 KB)
    Freely Available from IEEE
  • Message from the General Chair

    Publication Year: 2013, Page(s): xviii
    Request permission for commercial reuse | PDF file iconPDF (95 KB) | HTML iconHTML
    Freely Available from IEEE
  • Message from the Program Chairs

    Publication Year: 2013, Page(s): xix
    Request permission for commercial reuse | PDF file iconPDF (78 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2013, Page(s): xx
    Request permission for commercial reuse | PDF file iconPDF (85 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2013, Page(s): xxi
    Request permission for commercial reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • Program Subcommittee

    Publication Year: 2013, Page(s):xxii - xxv
    Request permission for commercial reuse | PDF file iconPDF (120 KB)
    Freely Available from IEEE
  • Additional Reviewers

    Publication Year: 2013, Page(s):xxvi - xxvii
    Request permission for commercial reuse | PDF file iconPDF (101 KB)
    Freely Available from IEEE
  • Transient Fault Tolerant QDI Interconnects Using Redundant Check Code

    Publication Year: 2013, Page(s):3 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    Asynchronous logic is a promising technology for building the chip-level interconnect of multi-core systems. However, asynchronous circuits are vulnerable to faults. This paper presents a novel scheme to improve the robustness of asynchronous systems. Our first contribution is a fault tolerant delay-insensitive redundant check coding scheme named DIRC. Using DIRC in 4-phase 1-of-n quasi-delay-inse... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework

    Publication Year: 2013, Page(s):11 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (206 KB) | HTML iconHTML

    In this paper, we describe the procedure of the Global Interconnect and Control (GLIC) synthesis step in a system level synthesis framework to automatically generate GLIC logics from a scheduled SDF. The generated GLIC logics consist of control FSMs, interconnect and data buffers to glue existing function implementations to construct the system, which is modeled by the scheduled SDF. The experimen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

    Publication Year: 2013, Page(s):21 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB) | HTML iconHTML

    Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance. In this paper we designed a circuit switched NoC and compared that with packet switched NoC. By speculation and analys... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations

    Publication Year: 2013, Page(s):29 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (417 KB) | HTML iconHTML

    Parallelized kernels for operations research belong to the class of the diffused computations of Dijkstra and Scholten. They communicate through small, constant-length (or at least bounded length) messages and quickly reach congestion. FPGAs allow the creation of many-cores architectures and, because they are reconfigurable, can embed networks-on-a-chip (NoCs) that have been finely tuned for these... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoC

    Publication Year: 2013, Page(s):39 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    Low energy consumption is crucial for embedded systems, including the ones that employ tiled Multiprocessor Systems-on-Chip(MPSoC). Such systems often execute real-time applications consisting of several tasks synchronized in a data-flow manner and mapped over different MPSoC tiles. Energy can be saved by lowering the processor voltage and frequency, hence extending the application execution over ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs

    Publication Year: 2013, Page(s):48 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB) | HTML iconHTML

    Computer architectures have evolved to structures where communication has become an essential part of the system and most of it currently takes place inside the chip. The number of on-Chip cores and the available off-chip bandwidth is not growing at the same rate. This demands for the inclusion of more sophisticated memory hierarchies inside the chip to deal with off-chip latency and bandwidth pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors

    Publication Year: 2013, Page(s):56 - 59
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    The continuous increase of the number of cores in tiled chip-multi-processors (CMP) will prevent traditional electronic networks on chip (NoC) to maintain an acceptable tradeoff between performance and power consumption. Recent advances in silicon-photonics open new opportunities for fast and low-energy on-chip interconnections but specific design and tuning is needed. This paper proposes Olympic,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Non-intrusive NoC DFS for Soft Real-Time Multimedia Applications

    Publication Year: 2013, Page(s):60 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    Multimedia applications executing on NoC-based multicore architectures demand high performance and power-efficiency. We propose a low-cost NoC DPM controller that performs dynamic frequency scaling on each NoC router by activating shared memory-based monitoring probes at different parallel application slices or using an independent sample rate. We evaluate our DFS module by running an MPEG4 transf... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation

    Publication Year: 2013, Page(s):64 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB) | HTML iconHTML

    The increase in complexity of electronic systems has opened the way to the use of different types of operating systems working together. The development of these systems requires simulation infrastructures where the entire system, including all its OSs, can be simulated, both for functional verification and performance evaluation. However, the generation of such simulation infrastructures with cur... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

    Publication Year: 2013, Page(s):68 - 72
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (601 KB) | HTML iconHTML

    In this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoC's data path component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are an... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPs

    Publication Year: 2013, Page(s):73 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB) | HTML iconHTML

    Chip Multiprocessors (CMPs) are widely used across many application domains. The processor allocator (PA) assigns one or a set of processors to execute an application's job. In order to be efficient, the allocation of jobs to processors should be fast, with low overhead, reduce fragmentation or be able to increase the number of allocated jobs. In this paper, we propose a new contiguous processor a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A General Framework for Average-Case Performance Analysis of Shared Resources

    Publication Year: 2013, Page(s):78 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB) | HTML iconHTML

    Contemporary embedded systems are based on complex heterogeneous multi-core platforms to cater to the increasing number of applications, some of which have (soft) real-time requirements. To reduce cost, resources are shared using diverse arbitration mechanisms, such as Time-Division Multiplexing (TDM), Static-Priority (SP), and Round-Robin (RR), depending on application and resource requirements. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Static Analysis Approach for Verification of Synchronization Correctness of SystemC Designs

    Publication Year: 2013, Page(s):89 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB) | HTML iconHTML

    In this paper a novel approach for verification of synchronization correctness of HLS-synthesizable SystemC designs is proposed. Synchronization correctness is formulated in terms of statement reach ability properties which makes it applicable to clocked, asynchronous and mixed designs. It allows automatic detection of deadlocks and concurrent data modification. Live lock detection and invariant c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calibration Error Bound Estimation in Performance Modeling

    Publication Year: 2013, Page(s):97 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (179 KB) | HTML iconHTML

    Performance modeling of embedded systems is used to explore the system-level design-space and compare a wide range of possible solutions with respect to their performance gain. Calibration and validation of the developed performance models help ensure that the performance predictions of these models are accurate. This paper presents formal definitions of the errors associated with the calibration ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.