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System Synthesis, 1999. Proceedings. 12th International Symposium on

Date 10-12 Nov. 1999

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  • Proceedings 12th International Symposium on System Synthesis

    Publication Year: 1999
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 1999, Page(s):v - vii
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1999, Page(s): 141
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    Freely Available from IEEE
  • Path-based edge activation for dynamic run-time scheduling

    Publication Year: 1999, Page(s):30 - 36
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    We present a tool that performs real time analysis and dynamic execution of software tasks in a mixed hardware-software system with a custom run time scheduler. The tasks in hardware and software have control flow constraints (precedence and alternative execution), resource constraints, relative timing constraints, and a rate constraint. The custom run time scheduler dynamically executes tasks in ... View full abstract»

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  • Catalyst: a DSIP design flow development in industry

    Publication Year: 1999, Page(s):122 - 127
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    The Motorola System on Chip Design Technologies (SoCDT) team aims at providing a system design environment for its customers. The Toulouse branch concentrates on design efforts incorporating DSP functionality. This is referred to as the Catalyst methodology. We found that in current systems, very often the software development cycle is longer than that of the silicon development. To ease the softw... View full abstract»

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  • A graph theoretic approach for design and synthesis of multiplierless FIR filters

    Publication Year: 1999, Page(s):94 - 99
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    We present a novel approach which can be used to obtain multiplierless implementations of finite impulse response (FIR) digital filters. The main idea is to reorder filter coefficients such that an implementation based on differential coefficients requires only a few adders. We represent this problem using a graph in which vertices represent the coefficients and edges represent the resources requi... View full abstract»

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  • Pre-fetching for improved core interfacing

    Publication Year: 1999, Page(s):51 - 55
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals. However, this separation can lead to a performance penalty when reading a core's internal registers. We introduce pre-fetching, which is analogous to caching, as a techniq... View full abstract»

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  • Bit-width selection for data-path implementations

    Publication Year: 1999, Page(s):114 - 119
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine the bandwidths of the resources required for a data-path implementation. We present a novel approach based on interval computations that provides, not only guaranteed range estimates that take into account dependencies bet... View full abstract»

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  • Efficient scheduling of DSP code on processors with distributed register files

    Publication Year: 1999, Page(s):100 - 106
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in the paper analyses the combination of lim... View full abstract»

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  • A framework for scheduling and context allocation in reconfigurable computing

    Publication Year: 1999, Page(s):134 - 140
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Reconfigurable computing is emerging as a viable design alternative to implement a wide range of computationally intensive applications. The scheduling problem becomes a really critical issue in achieving the high performance that these kind of applications demand. The paper describes the different aspects regarding the scheduling problem in a reconfigurable architecture. We also propose a general... View full abstract»

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  • System synthesis of synchronous multimedia applications

    Publication Year: 1999, Page(s):128 - 133
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Modern system design is being increasingly driven by applications such as multimedia and wireless sensing and communications, which all have intrinsic quality of service (QoS) requirements, such as throughput, error-rate, and resolution. One of the most crucial QoS guarantees that the system has to provide is the timing constraints among the interacting media (synchronization) and within each medi... View full abstract»

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  • Event-driven power management of portable systems

    Publication Year: 1999, Page(s):18 - 23
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The policy optimization problem for dynamic power management has received considerable attention in the recent past. We formulate policy optimization as a constrained optimization problem on continuous-time semi-Markov decision processes (SMDP). SMDPs generalize the stochastic optimization approach based on discrete-time Markov decision processes (DTMDP) presented in the earlier work by relaxing t... View full abstract»

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  • A buffer merging technique for reducing memory requirements of synchronous dataflow specifications

    Publication Year: 1999, Page(s):78 - 84
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Synchronous Dataflow, a subset of dataflow has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem during software synthesis from SDF specifications is the minimization of the memory used by the target code. We develop a powerful formal technique called buffer merging that attempts to overlay buffers in the SDF graph system... View full abstract»

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  • Compressed code execution on DSP architectures

    Publication Year: 1999, Page(s):56 - 61
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Decreasing the program size has become an important goal in the design of embedded systems targeted to mass production. This problem has led to a number of efforts aimed at designing processors with shorter instruction formats (e.g. ARM Thumb and MIPS16), or that can execute compressed code (e.g. IBM CodePack PowerPC). Much of this work has been directed towards RISC architectures though. This pap... View full abstract»

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  • Automatic architectural synthesis of VLIW and EPIC processors

    Publication Year: 1999, Page(s):107 - 113
    Cited by:  Papers (25)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    The paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing (EPIC) processor architectures starting from an abstract specification of their desired functionality. The process of architecture design makes concrete decisions regarding the number and types of functional units, number of read... View full abstract»

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  • Exploration and synthesis of dynamic data sets in telecom network applications

    Publication Year: 1999, Page(s):85 - 91
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    We present a novel exploration and optimization method to select customized implementations for dynamic data sets, as encountered in telecom network, database and multimedia applications. Our method fits in the context of embedded system synthesis for such applications, and enables us to further raise the abstraction level of the initial specification, where dynamic data sets can be specified with... View full abstract»

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  • Loop scheduling and partitions for hiding memory latencies

    Publication Year: 1999, Page(s):64 - 70
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    Partition scheduling with prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is first divided into regular partitions. Then two parts of the schedule, the ALU part and the memory part, are produced and balanced to produce an overall schedule with high throughput. These two parts are executed simulta... View full abstract»

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  • Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs

    Publication Year: 1999, Page(s):38 - 43
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    In order to cope with the ever increasing complexity of today's application specific integrated circuits, a building block based design methodology is established. The system is composed of high level building blocks, of which some are reused from previous designs while others might have been created by behavioral synthesis. In data flow oriented designs, these blocks usually have complex non-matc... View full abstract»

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  • Loop alignment for memory accesses optimization

    Publication Year: 1999, Page(s):71 - 77
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    Portable or embedded systems allow more and more complex applications like multimedia today. These applications and submicronic technologies have made the power consumption criterium crucial. We propose new techniques thanks to which we can optimize the behavioral description of an integrated system before the hardware/software partitioning (codedesign). These transformations are performed on &ldq... View full abstract»

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  • Real-time task scheduling for a variable voltage processor

    Publication Year: 1999, Page(s):24 - 29
    Cited by:  Papers (27)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    The paper presents a real time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks with a low supply voltage leads to drastic power reduction. However, reducing the supply voltage may violate real time constraints. We propose a scheduling technique which simultaneously assigns both CPU time and a supply vo... View full abstract»

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  • RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions

    Publication Year: 1999, Page(s):44 - 50
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    Reservation tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditional these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual specification of such conflict information i... View full abstract»

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  • Middleware techniques and optimizations for real-time, embedded systems

    Publication Year: 1999, Page(s):12 - 16
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    Due to constraints on footprint, performance, and weight/power consumption, real time, embedded system software development has historically lagged mainstream software development methodologies. As a result, real time, embedded software systems are costly to evolve and maintain. Moreover, they are often so specialized that they cannot adapt readily to meet new market opportunities or technology in... View full abstract»

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