2013 IEEE 19th International On-Line Testing Symposium (IOLTS)

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• [Front matter]

Publication Year: 2013, Page(s):i - xviii
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• Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead

Publication Year: 2013, Page(s):1 - 6
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This paper introduces a framework that tackles the costs in area and energy consumed by methodologies like spatial or temporal redundancy with a different approach: given an algorithm, we find a transformation in which part of the computation involved is transformed into memory accesses. The precomputed data stored in memory can be protected then by applying traditional and well established ECC al... View full abstract»

• Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

Publication Year: 2013, Page(s):7 - 12
Cited by:  Papers (2)
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A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under vari... View full abstract»

• Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus

Publication Year: 2013, Page(s):13 - 18
Cited by:  Papers (3)
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Serial communications protocols used in automotive systems must comply with different levels of robustness. Some subsystems in charge of n on-critical tasks are composed of cheaper and non-fault tolerant elements. As Single Event Upsets also affect these sub-systems, a complete analysis of heir robustness could highlight the critical elements and point out the possible solutions, such as selective... View full abstract»

• Highly-reliable integer matrix multiplication via numerical packing

Publication Year: 2013, Page(s):19 - 24
Cited by:  Papers (3)
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The generic matrix multiply (GEMM) routine comprises the compute and memory-intensive part of many information retrieval, relevance ranking and object recognition systems. Because of the prevalence of GEMM in these applications, ensuring its robustness to transient hardware faults is of paramount importance for highly-efficientlhighly-reliable systems. This is currently accomplished via error cont... View full abstract»

• Integrating embedded test infrastructure in SRAM cores to detect aging

Publication Year: 2013, Page(s):25 - 30
Cited by:  Papers (2)
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One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging dur... View full abstract»

• NBTI aging tolerance in pipeline based designs NBTI

Publication Year: 2013, Page(s):31 - 36
Cited by:  Papers (1)
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Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented... View full abstract»

• Variability-aware and fault-tolerant self-adaptive applications for many-core chips

Publication Year: 2013, Page(s):37 - 42
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The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on ... View full abstract»

• Increasing fault coverage during functional test in the operational phase

Publication Year: 2013, Page(s):43 - 48
Cited by:  Papers (1)
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A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly describe fault coverage figures to be achieved. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation ex... View full abstract»

• Investigating the limits of AVF analysis in the presence of multiple bit errors

Publication Year: 2013, Page(s):49 - 54
Cited by:  Papers (3)  |  Patents (1)
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We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up ... View full abstract»

• Timing vulnerability factors of sequential elements in modern microprocessors

Publication Year: 2013, Page(s):55 - 60
Cited by:  Papers (3)
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An efficient and novel technique for computing timing vulnerability factors (TVF) in modern complex synchronous designs is introduced, where all key inputs are based on static timing data readily available in most design databases. The benefits of TVF for modern microprocessors and strategies to reduce TVF, and hence the overall soft error rate (SER), are presented. View full abstract»

• Accelerating post silicon debug of deep electrical faults

Publication Year: 2013, Page(s):61 - 66
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With the growing complexity of current designs and shrinking time-to-market, traditional ATPG methods fail to detect all electrical faults in the design. Debug teams have to spend considerable amount of time and effort to identify these faults during post silicon debug. This work proposes off-chip analysis to speed-up the effort of identifying hard-to-find electrical faults that are not detected u... View full abstract»

• At-speed BIST for interposer wires supporting on-the-spot diagnosis

Publication Year: 2013, Page(s):67 - 72
Cited by:  Papers (3)
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Testing the speed of post-bond interposer wires in a 2.5-D stacked IC is essential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate t... View full abstract»

• A failure triage engine based on error trace signature extraction

Publication Year: 2013, Page(s):73 - 78
Cited by:  Papers (2)  |  Patents (1)
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The ever growing demand for functionally robust and error-free industrial electronics necessitates the development of techniques that will prohibit the propagation of functional errors to the final tape-out stage. This paramount requirement in the semiconductor world is imposed by the equivocal observation that functional errors slipping to silicon production introduce immense amounts of cost and ... View full abstract»

• A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors

Publication Year: 2013, Page(s):79 - 84
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Nowadays, Software-Based Self-Test (SBST) is growing in importance especially in the on-line test scenario for safety critical systems such as automotive. This paper concentrates on the coverage by SBST of those faults in the scan chain that can impact the behavior of the embedded processor while working in its application field. A technique is described that is able to systematically tackle these... View full abstract»

• Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery

Publication Year: 2013, Page(s):85 - 91
Cited by:  Papers (4)
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Cosmic radiation induced soft errors have emerged as a key challenge in computer system design. The exponential increase in the transistor count will drive the per chip fault rate sky high. New techniques for detecting errors in the logic and memories that allow meeting the desired failures in-time (FIT) budget in future chip multiprocessors (CMPs) are essential. Among the two major contributors t... View full abstract»

• Error detection encoding for multi-threshold capture mechanism

Publication Year: 2013, Page(s):92 - 97
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The crosstalk induced delays have become a significant bottleneck in deep sub-micron communication. The encoding techniques proposed in existing literature, that cope with crosstalk while providing error detection capabilities require significantly high redundancy to achieve the goal. It is shown in recent publications that the effect of crosstalk can be mitigated by using multiple threshold volta... View full abstract»

• Exploiting the debug interface to support on-line test of control flow errors

Publication Year: 2013, Page(s):98 - 103
Cited by:  Papers (3)
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Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed t... View full abstract»

• A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES

Publication Year: 2013, Page(s):104 - 109
Cited by:  Papers (3)
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The Advanced Encryption Standard (AES) is one of the most widespread encryption techniques used by millions of users worldwide. Although AES was designed to withstand linear or differential attacks, the security of encrypted messages is not guaranteed. Bit flips occurring during the encryption due to runtime failures or purposely invoked by an attacker are a major security concern and can signific... View full abstract»

• Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism

Publication Year: 2013, Page(s):110 - 115
Cited by:  Papers (9)
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Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we study the effect ... View full abstract»

• Embedded high-precision frequency-based capacitor measurement system

Publication Year: 2013, Page(s):116 - 121
Cited by:  Papers (4)
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This paper presents a direct way to measure the electrical value of capacitors embedded in a circuit using a ring-oscillator. A calibration system ensures robustness towards temperature, power supply and process variations. The measurement is largely automated to minimize the use of external instrumentation and to speed-up the measurement process while giving a digital signature of the capacitor v... View full abstract»

• Real-time checking of linear control systems using analog checksums

Publication Year: 2013, Page(s):122 - 127
Cited by:  Papers (6)
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In the recent past, there has been a proliferation of complex control problems in sensor network design, multi-agent systems such as autonomous vehicles and robotics, to name a few. While prior research has focused on the design of optimal controllers for real-time systems, in the future it will become increasingly difficult to perform periodic maintenance of such systems due to their mobile and a... View full abstract»

• Perturbation-immune radiation-hardened PLL with a switchable DMR structure

Publication Year: 2013, Page(s):128 - 132
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This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is detecting' and switching' instead of... View full abstract»

• Scanning the strength of a test signal to monitor electrode degradation within bio-fluidic microsystems

Publication Year: 2013, Page(s):133 - 138
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Lab-on-Chip devices are complex multifunctional heterogeneous microsystems that have the potential to strongly influence advances in important areas such as pharmacology, security, and environmental analysis. High reliability requirements in many of these microsystems are crucial which makes test more challenging especially given the need to validate multiple multi-domain interfaces and realise on... View full abstract»

• Hierarchical RTL-based combinatorial SER estimation

Publication Year: 2013, Page(s):139 - 144
Cited by:  Papers (10)
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With increased device integration and a gradual trend toward higher operating frequencies, the effect of radiation induced transients in combinatorial logic (SETs) can no longer be ignored. Electrical, logical and temporal masking prevent the majority of SETs from becoming functional failures. Current work on SET analysis starts from a gate-level circuit representation, however, in an industrial d... View full abstract»