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Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on

Date 24-27 June 2013

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Displaying Results 1 - 25 of 93
  • [Front cover]

    Publication Year: 2013 , Page(s): 1 - 2
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  • Table of contents

    Publication Year: 2013 , Page(s): iii - xii
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  • Welcome

    Publication Year: 2013 , Page(s): xiii - xxii
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  • Author index

    Publication Year: 2013 , Page(s): 353 - 356
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  • CMOS 8-channel frequency division multiplexer for 9.4 T magnetic resonance imaging

    Publication Year: 2013 , Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    We present a CMOS 8-channel frequency division multiplexer (FDM) to interface a phased array of micro coils for 9.4 T (400 MHz Larmor precession frequency ω0) for magnetic resonance imaging (MRI). The integrated multiplexer contributes towards a solution to achieve phased arrays with a massive number of coils without unnecessarily increasing system complexity, the size of hardware, and cost. The multiplexer is designed using commercially available 0.35 μm CMOS technology and consists of five major components: a low-noise amplifier (LNA), a frequency mixer, a voltage-controlled oscillator (VCO), a bandpass filter (BPF), and an adding operational amplifier. The maximum gain of a single channel is 79 dB, and the input referred noise is 1.4 nV/√Hz. The die area of the multiplexer is approximately 8 mm2, and requires 300 mA from a 3.3 V source. View full abstract»

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  • Comparison of high-voltage linear transmitter topologies for ultrasound CMUT applications

    Publication Year: 2013 , Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (411 KB) |  | HTML iconHTML  

    In this paper, we present a comparison of high-voltage linear transmitter circuits for driving capacitive micro-machined ultrasound transducers (CMUTs). CMUTs are emerging transducer elements in ultrasound imaging applications. Two different circuit topologies for the high-voltage linear transmitter with a 40 V peak-to-peak output voltage are compared. We compare the two designs based on total harmonic distortion, power consumption, bandwidth and area for same voltage gain. The designs are done in AMS 0.18 μm technology, and utilize Si LDMOS device for a high-voltage output. View full abstract»

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  • Bluetooth transceiver modeling using SystemC-AMS

    Publication Year: 2013 , Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    This paper presents the high-level modeling and simulation of a GFSK RF transceiver for a Bluetooth Low Energy (BLE) system. This model, written in SystemC-AMS (SCAMS) permits a simple integration within the existing system digital environment written in SystemC-TLM, which enables a global system simulation to obtain the system performance (e.g. Bit-Error-Rate (BER) or Packet- Error-Rate (PER)) related to the power and energy consumption. View full abstract»

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  • Design of mixers for a 130-GHz transceiver in 28-nm CMOS

    Publication Year: 2013 , Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (462 KB) |  | HTML iconHTML  

    A compact and 3-dB bandwidth of 118-145-GHz Gilbert-cell mixer for up-conversion and a 1-dB bandwidth of 106-143-GHz image-rejection (IR) resistive mixer for down-conversion are designed for a 130-GHz transceiver in 28-nm CMOS technology. A wide 10-GHz intermediate frequency (IF) tuning range is obtained for both mixers. The simulated results show a +1.6-dB conversion gain for the Gilbert-cell mixer with a layout size of 720×633 μm2 and 6.1 mW of DC power consumption. An 11-dB conversion loss and 30-dB IR ratio are simulated for the resistive mixer with a layout size of 845×794 μm2. The simulated 1-dB output compression point is -8 dBm for the Gilbert-cell mixer and 1-dB input compression point is +9 dBm for the resistive mixer. View full abstract»

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  • A 12dBm IIP3 reconfigurable mixer for high/low band IR-UWB receivers

    Publication Year: 2013 , Page(s): 81 - 84
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage. View full abstract»

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  • Phase Noise comparative analysis of LC oscillators in 28-nm CMOS through the Impulse Sensitivity Function

    Publication Year: 2013 , Page(s): 85 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    Comparative Phase Noise (PN) analysis of Hartley, Colpitts and Cross-coupled LC oscillators at 10 GHz in 28-nm CMOS technology is reported. The results of the PN direct plots in the Cadence-SpectreRF design environment are compared with the results obtained by the Impulse Sensitivity Function (ISF). The steps for deriving accurately the ISF are reported and discussed. The results show a very good agreement in a set of conditions, and confirm that the LC cross-coupled differential oscillator exhibits superior PN performance with respect to Colpitts and Hartley, and also that Colpitts exhibits slightly superior performance with respect to Hartley. View full abstract»

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  • Graph Coverage: An FPGA-targeted implementation

    Publication Year: 2013 , Page(s): 129 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB) |  | HTML iconHTML  

    Classification systems specifically designed to deal with fully labeled graphs are gaining importance in many application fields. The main computational bottleneck in such systems is the dissimilarity measure between pairs of graphs. In this paper we propose to accelerate in hardware such computations, relying on the Graph Coverage as the core inexact graph matching procedure, targeting the design to FPGA as an inexpensive way to design specific co-processing devices. A comparison in terms of computational time between the proposed system and a software implementation on a standard workstation shows encouraging results. View full abstract»

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  • Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching Networks

    Publication Year: 2013 , Page(s): 133 - 136
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (633 KB) |  | HTML iconHTML  

    Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design. View full abstract»

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  • Direct Digital Frequency Synthesizers implemented on high end FPGA devices

    Publication Year: 2013 , Page(s): 137 - 140
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    Direct Digital Frequency Synthesizer (DDFS) circuits are routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed and optimized for ASIC (Application Specific Integrated Circuits) implementations. Nowadays, FPGA devices are frequently chosen as target for digital circuits. This paper presents the FPGA implementation of state of the art DDFS architectures and compares their performance providing hints on optimal design as a function of the chosen performance parameter. View full abstract»

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  • A very low OSR 90nm 1MS/s incremental ΣΔ ADC

    Publication Year: 2013 , Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1886 KB) |  | HTML iconHTML  

    A calibration free, high resolution second-order multichannel Incremental A-to-D-Converter with multi-level quantizer is presented. The system is designed for biomedical application and combines the advantages of low oversampling ratio with SC design solution, like multi bit topology and accurate opamp design. An optimal decimation filter to minimize the weighted sum of thermal and quantization noise is used. In this paper is presented the schematic level implementation of the system in a 1.2 V 90 nm CMOS Technology and the preliminary simulation shows a 56.4 dB signal-to-noise-distortion within a 500 kHz bandwidth at a 16 MHz sample frequency. View full abstract»

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  • Variable-step 12-bit ADC based on counter ramp recycling architecture suitable for CMOS imagers with column-parallel readout

    Publication Year: 2013 , Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    A 12-bit counter ramp recycling analog-to-digital converter (ADC) is proposed, which can be configured in a single-step mode for achieving high conversion accuracy as well as in various multi-step modes for yielding high conversion speed. A unique ADC circuit realization is used for the different modes of operation, while a digital control unit is responsible for providing the necessary control signals to the ADC. Similar to common counter ramp architectures, the proposed implementation is suitable for column-parallel readout owing to its simplicity. The proposed variable-step recycling ADC is implemented in a 0.18μm CMOS technology from UMC. Simulation results show good agreement with the expected trade-off between speed and accuracy, which is common to all conventional ADCs. View full abstract»

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  • An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments

    Publication Year: 2013 , Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB) |  | HTML iconHTML  

    A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures A-to-D architectures, compensating slope deviations due to technological/electrical reasons. Moreover, the calibration circuit shares the same analog circuits of the A-to-D converter, requiring only a small additional power budget and logic for the implementation. The calibration circuit has been validated, testing the overall A-to-D converter after the calibration. A 12 steps binary search is required to calibrate the A-to-D converter (about 2.5ms). This calibration circuit is able to guarantee an 11bits accuracy, in the worst case simulation corner. The technology used is a 65 nm CMOS. The clock frequency has been set to 20 MHz and the power consumption is about 400 μW. View full abstract»

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  • Investigation of two-point modulation to increase the GFSK data rate of PLL-based wireless transceivers of wireless sensor nodes

    Publication Year: 2013 , Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB) |  | HTML iconHTML  

    Gaussian Frequency-shift-keying (GFSK) is a widely used modulation scheme in state-of-the-art wireless transceivers. Most often a phase-locked-loop (PLL) is utilized for carrier generation and GFSK modulation. Using this architecture the maximum applicable data rate is limited by the PLL's bandwidth. This paper investigates the possibility of using two-point modulation in order to be able to choose the GFSK data rate independently of the bandwidth. The most important aspect of two-point modulation is the mismatch of the gain of the two modulation paths. Two methods which allow close gain matching are presented in this work. Time-domain simulations using Verilog-A models of the analog and RTL models of the digital building blocks of a wireless transceiver have been carried out and confirm the capability of extending its GFSK data rate to 1Mbps while using a PLL closed-loop bandwidth of 44.5 kHz. View full abstract»

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  • Transient analysis applying S-parameters as operators

    Publication Year: 2013 , Page(s): 93 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (146 KB) |  | HTML iconHTML  

    We propose a calculation method for transient analysis of linear time-invariant systems basing on the Mikusinski operator. Since signal-flow charts and scattering parameters (S-parameters) are used to describe the networks to analyze, the method is very vivid. The applied S-parameters form operators describing transmission and reflection of power waves from one node to an other of the network's signal-flow chart. Although the usage of operators exhibits some similarities to the Laplace transform, the effect of the operators is interpreted in time domain, and a signal transformation is not required. Thus, the presented calculation method is suitable to vividly analyze dynamic processes on electrical lines. View full abstract»

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  • Design of a W-Band 2-bit differential CMOS phase shifter

    Publication Year: 2013 , Page(s): 97 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    This paper presents the design of a W-Band I-Q phase shifter and the corresponding simulation results in 28-nm CMOS technology. The design of passive components like a 90° hybrid and transformers needed to realize differential I-Q operation is shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The simulated input and output matching are better than -10 dB, and the maximum phase error is roughly 10° with a maximum output imbalance of 0.5 dB at 90 GHz using a 1-V supply voltage. The total power consumption is 41 mW and the die area is 0.46 mm2. View full abstract»

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  • Random interleaved pipeline countermeasure against power analysis attacks

    Publication Year: 2013 , Page(s): 145 - 148
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    An RTL countermeasure intended to protect the AddRoundKey and SubByte steps of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on first order CPA attacks confirmed the effectiveness of the proposed countermeasure, especially in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the absolute value of correlation function is embedded in the measured noise floor and there are no peaks able to reveal the encryption key. View full abstract»

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  • Fast constant time memory allocator for inter task communication in ultra low energy embedded systems

    Publication Year: 2013 , Page(s): 149 - 152
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    Modern microcontrollers provide enough processing power to benefit from the advantages of multitasking schedulers or operating systems even in the area of small, battery based or energy self-sustaining devices. Many of these devices communicate with other devices via different interfaces. For a multitasking operating system, communication means to collect individual bytes in memory blocks and to transport these blocks between tasks. This paper describes how to use a combination of memory pools and memory headers to provide a fast, constant time memory allocator with low internal fragmentation. The proposed memory allocator is fast enough and has so few internal fragmentation, that it is applicable even in ultra low energy embedded systems with few kilobytes of ram. It can provide memory blocks of equal size at high frequency. View full abstract»

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  • A new decoding solution for the asynchronous sigma delta modulator

    Publication Year: 2013 , Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (530 KB) |  | HTML iconHTML  

    A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this circuit is to achieve a high resolution with a low frequency sampling clock, which is suitable for the ultra-low power applications. The proposed circuit is designed in 0.35um. Spectre simulations, show an 11-bit resolution is realized with 0.06LSB integral non-linearity and 0.04LSB differential non-linearity. The simulated power consumption is below16uW from a dual 0.6 V supply voltage. View full abstract»

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  • A low-power, continuous-time sigma-delta modulator for MEMS microphones

    Publication Year: 2013 , Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    This paper presents a continuous-time ΣΔ ADC for MEMS microphone integrated interface applications. The ΣΔ modulator features a 3rd-order loop filter realized with only two operational amplifiers to reduce power consumption. It exploits a 15-level quantizer and 3-MHz sampling frequency to minimize the impact of clock jitter. The proposed architecture can handle an excess loop delay of half period of the sampling clock. The ΣΔ modulator, simulated at transistor-level, performs a 105.5dB A-weighted dynamic range (DR) and a 100.8 dB signal-to-noise-and-distortion ratio (SNDR) at -2 dBFS. The device operates from a single 1.8 V and consumes 200 μW. View full abstract»

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  • System-level power optimization for a ΣΔ D/A converter for hearing-aid application

    Publication Year: 2013 , Page(s): 75 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    This paper deals with a system-level optimization of a back-end of audio signal processing chain for hearing-aids, including a sigma-delta modulator digital-to-analog converter (DAC) and a Class D power amplifier. Compared to other state-of-the-art designs dealing with sigma-delta modulator design for audio applications we take the maximum gain of the modulator noise transfer function (NTF) as a design parameter. By increasing the maximum NTF gain the cutoff frequency of modulator loop filter is increased which lowers the in-band quantization noise but also lowers the maximum stable amplitude (MSA). This work presents an optimal compromise between these. Increased maximum NTF gain combined with a multi bit quantizer in the modulator allows lower oversampling ratio (OSR) and results in considerable power savings while the audio quality is kept unchanged. The proposed optimization impacts the entire hearing-aid audio back-end system resulting in less hardware and power consumption in the interpolation filter, in the sigma-delta modulator and reduced switching rate of the Class D output stage. View full abstract»

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  • Impact of PA class on reconstruction filters sizing for a WCDMA base station LINC transmitter

    Publication Year: 2013 , Page(s): 101 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    The LInear amplification with Nonlinear Component transmitter is a high power efficient architecture for radio communication systems. Nevertheless, this architecture is sensitive to mismatches between the two paths and its efficiency performances are dependent on the power amplification stage topology. Additively, careful attention has to be paid to baseband performances in terms of sampling rate, Digital to Analog Converters (DACs) resolution, reconstruction filter bandwidth. In this paper, we present the specification of the reconstruction filters for a single carrier WCDMA 3GPP base station transmitter and this, according to the Power Amplifier (PA) class (switched mode (SMPA) or AB class). We address the impact of the class of the PAs on the overall performances and on the reconstruction filters specifications. Admissible time delays and gain mismatches between the two paths will also be quantified. View full abstract»

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