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Memory Workshop (IMW), 2013 5th IEEE International

Date 26-29 May 2013

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Displaying Results 1 - 25 of 58
  • Device considerations of planar NAND flash memory for extending towards sub-20nm regime

    Publication Year: 2013 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (261 KB) |  | HTML iconHTML  

    Device considerations of planar NAND flash memory for extending towards sub-20nm regime have been reviewed. A transient deep-depletion phenomenon of p-type floating gate, which affects the program efficiency of a scaled device, is described. The endurance of the p-type floating gate has been improved with an aid of hole compensation on the charge trapping. Meanwhile, solutions are required to overcome the lowering of the boosting potential by the BTBT generation with increased lateral electric field between the channels as well as the BTBT generation with increased vertical electric field. Furthermore, the conventional DIBL effect also significantly affects VT shift on the scaled-NAND string. Regarding the reliability, the electric field crowding on the top of the floating gate should be relieved and it has been revealed that the endurance behavior has been changed by the increase of edge tunneling current during the erase operation. View full abstract»

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  • [Title page]

    Publication Year: 2013 , Page(s): 1
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    Freely Available from IEEE
  • Engineering a planar NAND cell scalable to 20nm and beyond

    Publication Year: 2013 , Page(s): 5 - 8
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1402 KB) |  | HTML iconHTML  

    Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell. View full abstract»

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  • 2013 5th IEEE International Memory Workshop (IMW) [Copyright notice]

    Publication Year: 2013 , Page(s): 1
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    Freely Available from IEEE
  • Advancement in Charge-Trap Flash memory technology

    Publication Year: 2013 , Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1610 KB) |  | HTML iconHTML  

    Charge-trap Flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit® charge-trap technology has been the industry benchmark for NOR Flash for more than a decade, spanning six generations of scaling. More recently Heterogeneous Charge Trap (HCT)™ NAND Flash as well as embedded Charge Trap (eCT)™ NOR Flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3D charge-trap Flash will emerge and further extend the density-growth trend. View full abstract»

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  • Summary of events

    Publication Year: 2013 , Page(s): 1 - 3
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  • Phase Change Memories have taken the field

    Publication Year: 2013 , Page(s): 13 - 16
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1357 KB) |  | HTML iconHTML  

    Phase Change Memories (PCM) have been developed since few years and now they are in volume production, thus demonstrating the maturity of the technology. State of the art access time of 85ns, read throughput 266MB/s and write throughput 9MB/s combined with data retention, single bit alterability, execution in place and good cycling performance enables traditional NVM utilizations but also already opened applications in LPDDR field. In the following the technology status will be reviewed and future applications and development lines will be drawn. View full abstract»

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  • Table of contents

    Publication Year: 2013 , Page(s): 1 - 5
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    Freely Available from IEEE
  • Device performance in a fully functional 800MHz DDR3 spin torque magnetic random access memory

    Publication Year: 2013 , Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    With the recent sampling of Everspin Technologies spin torque magnetoresistive random access memory (ST-MRAM), the performance gap between the high speed volatile memories of SRAM and DRAM and the non-volatile memories of hard disk drives (HDD), Flash and PCRAM has been significantly reduced. We have demonstrated a fully functional 64Mb DDR3 ST-MRAM built on 90nm CMOS technology. This device combines the high speed operation of DDR3 with 1.6 GT/s (DDR3-1600) and the endurance of DRAM with the non-volatility of HDD, Flash or PCRAM. Full functionality has been verified from 0°C to 70°C at up to 800MHz using a March6N pattern with full memory cycling and 0 fails. The memory element used was a magnetic tunnel junction (MTJ) with CoFeB-based magnetic layers and an MgO tunnel barrier. This paper compares the performance of ST-MRAM in speed, non-volatility and endurance with the various memory solutions available on the market. View full abstract»

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  • Author index

    Publication Year: 2013 , Page(s): 1 - 3
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  • Memory scaling: A systems architecture perspective

    Publication Year: 2013 , Page(s): 21 - 25
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB) |  | HTML iconHTML  

    The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques. In this paper, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we survey three key solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system, 2) designing a memory system that employs emerging memory technologies and takes advantage of multiple different technologies, 3) providing predictable performance and QoS to applications sharing the memory system. We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory. View full abstract»

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  • 90nm WAl2O3TiWCu 1T1R CBRAM cell showing low-power, fast and disturb-free operation

    Publication Year: 2013 , Page(s): 26 - 29
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (517 KB) |  | HTML iconHTML  

    In this paper we demonstrate excellent memory performances of a 90nm CMOS-friendly WAl2O3TiWCu CBRAM cell integrated in a 1T1R configuration and withstanding the back-end of line thermal budget of 400°C. The cell exhibits low-power and highly controlled set and reset operations, allowing reversible multilevel programming controlled by both the set current and the reset voltage. Low-voltage (<;3V) operation is obtained down to 10ns-long write pulse both for set and reset, and allowing >106 write endurance with a 2-decade memory window. State stability is assessed up to 125°C. Moreover, due to low slope of the voltage-log(time) relationship the cell also shows excellent voltage-disturb immunity assessed up to +/-0.5V and extrapolated to 10 years. View full abstract»

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  • Intrinsic switching variability in HfO2 RRAM

    Publication Year: 2013 , Page(s): 30 - 33
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1039 KB) |  | HTML iconHTML  

    In this work, we present a systematic electrical characterization of TiNHfO2HfTiN RRAM elements from the variability perspective. Variability of both programmed resistance values and switching triggering voltages has been evaluated on small scaled cells in a wide operating current range (2μA till 500μA's), for different oxide stacks, in DC and pulsed conditions. For the first time device-to-device and cycle-to-cycle variability are thoroughly compared as well as the impact of different oxygen vacancy profiles. Increase of variability in low current operation is also elucidated. View full abstract»

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  • Consideration of conductive filament for realization of low-current and highly-reliable TaOx ReRAM

    Publication Year: 2013 , Page(s): 34 - 37
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1829 KB) |  | HTML iconHTML  

    Characteristics and their origin of a conductive filament in TaOx ReRAM are investigated. The results of systematic experimentation demonstrate that the formation of a small conductive filament with high density of oxygen vacancies, achieved by controlling the oxygen content of the resistance-switching material and forming/set current, is the key to achieving low-current switching combined with long retention. View full abstract»

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  • Variability and failure of set process in HfO2 RRAM

    Publication Year: 2013 , Page(s): 38 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (719 KB) |  | HTML iconHTML  

    Resistive-switching memory (RRAM) may provide a scalable, low-power alternative to Flash memories for sub-10 nm technology nodes. Due to the atomic-size conductive filament (CF), however, switching variability due to few-defect migration is becoming one of the main concerns for RRAM scaling. This work addresses set-state variability in HfOx RRAM. Our study shows that variability increases at small CF size, which is quantitatively explained by defect-number fluctuations within a Poisson distribution. The set failure at relatively large CF sizes is then shown for the first time and explained by complementary switching (CS). Advanced program-verify schemes are needed to improve the distribution shape and allow reliable RRAM operation, e.g., in multilevel cell applications. View full abstract»

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  • Highly reliable ReRAM technology with encapsulation process for 20nm and beyond

    Publication Year: 2013 , Page(s): 42 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (997 KB) |  | HTML iconHTML  

    ReRAM cell performance and reliability have been improved through process optimization. Encapsulated ReRAM cell with SiN capping layer shows excellent endurance, read disturb, and retention characteristics. We demonstrated that effective oxygen barrier encapsulation is critical for keeping ReRAM performance in an aggressively scaled technology node. View full abstract»

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  • Stability conditioning to enhance read stability 10x in 50nm AlxOy ReRAM

    Publication Year: 2013 , Page(s): 44 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (614 KB) |  | HTML iconHTML  

    This study focuses on read stability after reset in 50nm AlxOy ReRAM. Unstable behaviors are characterized and a 2-part solution to reduce instability from 64 to 6% and read error from 8 to 0.2% is proposed. After conventional reset including verify, (i) a block-level low voltage sealing operation is followed by (ii) a stability check loop. View full abstract»

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  • Performance and reliability of Ultra-Thin HfO2-based RRAM (UTO-RRAM)

    Publication Year: 2013 , Page(s): 48 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    We report on the performance and reliability of the Hf/HfO2 RRAM cell with Ultra-Thin Oxide (UTO-RRAM). We show that cells with an oxide thickness of 3 nm have basic performance (including speed, switching voltages, and the on/off window) similar to that of the cells with reference oxide (5-10 nm thickness), while their operation requires a forming step at a voltage of only about 1.5 V for a 40 nm size. This performance can be further optimized by tuning the cap layer thickness. We also demonstrate endurance of at least 108 cy and observe failure modes similar to the reference cells. Endurance optimization needs to take into account, next to the stack structure and pulse characteristics, the target on/off states. UTO-RRAM retention is strongly temperature-activated, with a median cell extrapolating at 125°C/10 yr. Furthermore, we analyze in detail the on-state loss and show how emergence of tail bits relates to the strength (initial level) of the state. View full abstract»

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  • Modeling the effects of different forming conditions on RRAM conductive filament stability

    Publication Year: 2013 , Page(s): 52 - 55
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4159 KB) |  | HTML iconHTML  

    In order to identify the factors controlling the filament characteristics, we perform physics-based simulations of the inherently stochastic and difficult-to-control forming process using a statistical Monte-Carlo method to model the Hf-O bond-breakage, oxygen ion diffusion and vacancy-oxygen recombination. Simulation results well reproduce the experimental trends observed for the conductivity of the post-forming low resistance state under different forming conditions. It is shown that the distribution of the oxygen ions in the surrounding oxide during forming as well as local filament temperature and electrical field all affect the filament stability. View full abstract»

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  • Write stress reduction in 50nm AlxOy ReRAM improves endurance 1.4× and write time, energy by 17%

    Publication Year: 2013 , Page(s): 56 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (527 KB) |  | HTML iconHTML  

    Novel write verification methods are proposed to improve write speed, energy and endurance of resistive random access memory (ReRAM). Flexible write stress is implemented during reset w/ verification and set w/ verification, by which the pulse width or voltage can be decremented as well as incremented. Proposed reset w/ verification and set w/ verification methods are characterized by measuring 50nm AlxOy ReRAM devices and compared against conventional methods. Improvements of 1.9× average endurance increase, or 1.4× average endurance increase with 17% write time, the reset time plus set time decrease and 17% average write energy reduction are demonstrated. View full abstract»

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  • Highly scalable and manufacturable heterogeneous charge trap NAND technology

    Publication Year: 2013 , Page(s): 60 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1930 KB) |  | HTML iconHTML  

    For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product performance, reliability, and manufacturability demonstrated at the 43nm node, in conjunction with the planar cell architecture have laid the foundation for scaling to <; 20nm. View full abstract»

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  • SCM capacity and NAND over-provisioning requirements for SCM/NAND flash hybrid enterprise SSD

    Publication Year: 2013 , Page(s): 64 - 67
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (413 KB)  

    The required storage class memory (SCM) capacity and NAND over-provisioning (OP) for SCM/NAND hybrid enterprise solid state drive (SSD) are evaluated for various storage workloads. From the worst case simulations (hot and random data intensive workloads), it is found that less than 8% SCM/NAND capacity ratio with below 25% NAND OP is sufficient assuming SCM bit cost is 10-times as high as that of NAND. Other workloads with the exception of all-cold-data case can use less than 4% SCM/NAND capacity ratio with 100% NAND OP. According to the analyses, SCM tends to be cost-effective for the hot workload rather than the random one. Furthermore, the effect of NAND organization on the hybrid SSD write performance is considered. NAND organization with an 8-128KB page size and 1-8MB block size provides the best performance for the hot and random data intensive workloads. From the energy point of view, SCM/NAND hybrid SSD allows larger NAND page sizes compared with NAND-only SSD. View full abstract»

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  • A novel multilayer Inter-Gate Dielectric enabling up to 18V Program / Erase window for planar NAND flash

    Publication Year: 2013 , Page(s): 68 - 71
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (601 KB) |  | HTML iconHTML  

    The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20 nm node causes important loss of coupling factor. In order to recover the Program / Erase window, a Hybrid Floating Gate featuring a high work function metal on top of Si, together with a high-k Inter-Gate Dielectric are needed. In this paper, we develop a multilayer Inter-Gate Dielectric based on HfAlO and Al2O3, combined with a Si/TiN Hybrid Floating Gate. By optimizing the stack structure, a window as large as ~18V could be obtained. View full abstract»

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  • Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node

    Publication Year: 2013 , Page(s): 72 - 75
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (775 KB) |  | HTML iconHTML  

    A new program disturbance phenomenon appeared from sub 40nm-node NAND flash cell is presented firstly which is named as BTBT Leakage Burst by Channel Coupling (abbr. “Channel Coupling”). With scaling down, the neighboring program channel of 0V grabs strongly the boosted channel at program-inhibited active line not to rise up at the active sidewall and simultaneously, its potential at Si surface is tried to be raised by help of pass voltage. The competition induces the sharp band-bending and thereby sudden enhancement of BTBT leakage, resulting in suppressing channel boosting. In order to overcome “Channel Coupling” appeared at 1X-nm node as a scaling barrier, the air gap in shallow trench isolation is suggested and the effect of the air gap is verified by simulation. View full abstract»

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  • Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

    Publication Year: 2013 , Page(s): 76 - 79
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB) |  | HTML iconHTML  

    Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin. View full abstract»

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