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Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on

Date 7-11 Nov. 1999

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Displaying Results 1 - 25 of 111
  • 1999 IEEE/ACM International Conference on Computer-Aided Design. [Front Cover and Table of Contents]

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    Freely Available from IEEE
  • Marsh:min-area retiming with setup and hold constraints

    Page(s): 2 - 6
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    This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed version of G satisfying setup and hold constraints or reports that such a solution is not possible, in O(|V/sup 3/|log|V|log(|V|C)) steps, where |V| corresponds to number of gates in the circuit and C is equal to the number of registers in the circuit. This is the first polynomial time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues in to consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long-path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that technique are likely to be valid for improving the performance of the technique described in this paper. View full abstract»

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  • OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic

    Page(s): 7 - 13
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    The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. The OPTIMIST (OPTImal MInimization of STates) algorithm (R.M. Fuhrer et al., 1997) was the first general solution to this problem for synchronous finite state machines (FSMs). In this paper, we present the first solution for asynchronous FSMs. This paper makes two contributions. First, we introduce OPTIMISTA (OPTIMIST-Asynchronous), a new algorithm which guarantees optimum 2-level output logic for asynchronous FSMs. In asynchronous machines, output logic is often critical: it usually determines the machine latency. The algorithm is formulated as a binate constraint satisfaction problem, which is solved using a binate solver. The second contribution is a novel alternative result: the unreduced machine itself can be used directly to obtain minimum-cardinality output logic. Thus, this paper presents two approaches: using OPTIMISTA, which simultaneously performs state and logic minimization; or using no state reduction (if output logic cardinality is of sole interest). Extensions for literal optimization, targetted to multi-level logic, are also proposed. View full abstract»

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  • Bit-level arithmetic optimization for carry-save additions

    Page(s): 14 - 18
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    Addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in some datapaths in digital signal processing circuits). We first show that by relaxing the carry-save representation to allow for more than two signals per bit position, we gain flexibility in the bit-level implementation of CSA arrays that can be exploited to achieve a more efficient design. We then propose algorithms to optimize a single adder array at the bit-level. In addition, we proposed a heuristic to optimize a series of adder arrays that might occur in a datapath. We have applied our algorithms to the optimization of high-speed digital FIR filters and have achieved 15% to 30% savings (weighted cost) in the overall filter implementation array in comparison to the standard carry-save implementation. View full abstract»

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  • Attractor-repeller approach for global placement

    Page(s): 20 - 24
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    Traditionally, analytic placement has used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together. The result is a placement with a great deal of overlap among the cells. To reduce cell overlap, the methodology iterates between global optimization and repartitioning of the placement area. In this work, we added new attractive and repulsive forces to the traditional formulation so that overlap among cells is diminished without repartitioning the placement area. The superiority of our approach stems from the fact that our new formulations are convex and no hard constraints are required. A preliminary version of the new placement method is tested using a set of MCNC benchmarks and, on average, the new method achieved 3.96% and 7.6% reduction in wirelength and CPU time compared to TimberWolf v7.0 in the hierarchical mode. View full abstract»

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  • Cell replication and redundancy elimination during placement for cycle time optimization

    Page(s): 25 - 30
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    Presents a new timing-driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now, it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing-driven layout synthesis. Therefore, this paper presents a timing-driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool, and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques. View full abstract»

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  • Concurrent logic restructuring and placement for timing closure

    Page(s): 31 - 35
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    An algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each super-cell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm. View full abstract»

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  • Implicit enumeration of strongly connected components

    Page(s): 37 - 40
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    This paper presents a binary decision diagram (BDD) based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experiments suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency matrix of the graphs. View full abstract»

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  • Least fixpoint approximations for reachability analysis

    Page(s): 41 - 44
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    The knowledge of the reachable states of a sequential circuit can dramatically speed up optimization and model checking. However, since exact reachability analysis may be intractable, approximate techniques are often preferable. H. Cho et al. (1996) presented the machine-by-machine (MBM) and frame-by-frame (FBF) methods to perform approximate finite state machine (FSM) traversal. FBF produces tighter upper bounds than MBM; however, it usually takes much more time and it may have convergence problems. In this paper, we show that there exists a class of methods-least fixpoint approximations-that compute the same results as RFBF ("reached FBF", one of the FBF methods). We show that one member of this class, which we call "least fixpoint MBM" (LMBM), is as efficient as MBM, but provably more accurate. Therefore, the trade-off that existed between MBM and RFBF has been eliminated. LMBM can compute RFBF-quality approximations for all the large ISCAS-89 benchmark circuits in a total of less than 9000 seconds. View full abstract»

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  • Lazy group sifting for efficient symbolic state traversal of FSMs

    Page(s): 45 - 49
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    Proposes lazy group sifting for dynamic variable reordering during state traversal of finite state machines (FSMs). The proposed method relaxes the idea of pairwise grouping of the present state variables and their corresponding next state variables. This is done to produce better variable orderings during image computation without causing BDD (binary decision diagram) size blowup in the substitution of next state variables with present state variables at the end of image computation. Experimental results show that our approach is more robust in state traversal than the approaches that either unconditionally group variable pairs or never group them. View full abstract»

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  • Efficient manipulation algorithms for linearly transformed BDDs

    Page(s): 50 - 53
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    Binary decision diagrams (BDDs) are the state-of-the-art data structure in VLSI CAD, but, due to their ordering restriction, only exponential-sized BDDs exist for many functions of practical relevance. Linear transformations (LTs) have been proposed as a new concept to minimize the size of BDDs, and it is known that, in some cases, even an exponential reduction can be obtained. In addition to a small representation, the efficient manipulation of a data structure is also important. In this paper, we present polynomial-time manipulation algorithms that can be used for linearly transformed BDDs (LT-BDDs) analogously to BDDs. For some operations, like synthesis algorithms based on ITE (if-then-else), it turns out that the techniques known from BDDs can be directly transferred, while for other operations, like quantification and cofactor computation, completely different algorithms have to be used. Experimental results are given to show the efficiency of the approach. View full abstract»

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  • Noise analysis of non-autonomous radio frequency circuits

    Page(s): 55 - 60
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    Considers the important problem of noise analysis of non-autonomous nonlinear RF circuits in the presence of input signal phase noise. We formulate this problem as a stochastic differential equation and solve it in the presence of circuit white-noise sources. We show that the output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary-not cyclostationary (as would be predicted by traditional analyses). We also show that effect of the input signal phase noise is to act as additional white noise source. This result is derived using a full nonlinear analysis of the problem and cannot be predicted by traditional linear analysis-based techniques. Input signal phase noise can be an important portion of the overall output noise of the non-autonomous circuit. In our opinion, existing analyses have not considered this effect in a rigorous manner. We also relate this solution to results of the existing nonlinear time-domain and frequency-domain methods of noise analysis and point out the modifications required for the present techniques. We illustrate our technique using an example. View full abstract»

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  • New methods for speeding up computation of Newton updates in harmonic balance

    Page(s): 61 - 64
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    A new adaptive approach to solving large-dimension harmonic balance (HB) problems in RF circuit simulation is presented. The method is based on adjusting the order of the equation system according to the degree of nonlinearity of each node in the circuit. A block-diagonal preconditioner is used to construct an algorithm for order reduction during the iterative HB process. View full abstract»

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  • Design and optimization of LC oscillators

    Page(s): 65 - 69
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    Presents a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular, the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power. View full abstract»

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  • Modeling and simulation of the interference due to digital switching in mixed-signal ICs

    Page(s): 70 - 74
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    Introduces a methodology for the evaluation of the interference noise caused by digital switching activity in sensitive circuits of a mixed digital-analog chip. The digital switching activity is modeled stochastically as functions defined on Markov chains. The actual interference signal is obtained through the modulation of this discrete stochastic signal with real current injection patterns stored a priori in a pre-characterized library. The interference noise results from the propagation of these continuous stochastic signals through the linear network that models the chip power grid, substrate and relevant package parasitics. The interference noise power spectral density is computed by linear frequency-domain analysis. The methodology is implemented using advanced numerical techniques that are capable of tackling very large problems. View full abstract»

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  • Provably good algorithm for low power consumption with dual supply voltages

    Page(s): 76 - 79
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    The dual-voltage approach has emerged as an effective and practical technique for power reduction. In this paper, we explore power optimization with dual supply voltages under given timing constraints. By analyzing the relations among the timing slack, delay and power consumption in a given circuit, we relate the voltage-scaling power optimization to the maximal weighted independent set (MWIS) problem, which is polynomial-time solvable on a transitive graph. Then we develop a provably good lower-bound algorithm based on MWIS to generate the lower bound of the power consumption. Also, we propose a fast approach to predict the optimum supply voltages. The maximum power reduction is obtained by using a modified lower-bound algorithm with optimum voltages. Experimental results show that the resulting lower bound is tight for most circuits and that the estimated optimum supply voltage is exactly, or very close to, the best choice of actual voltages. View full abstract»

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  • A novel design methodology for high performance and low power digital filters

    Page(s): 80 - 83
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    Presents novel design methodologies which can be used to dramatically reduce the complexity of parallel implementations of digital FIR filters. These approaches are also applicable to IIR filters. Two ideas are presented. First, we remove the redundant computation by using a graph-theoretic framework in which we find the optimal re-ordering of computations for maximal computation sharing. Second, we present the novel approach of searching for a quantization which improves the computation sharing when the frequency-domain transfer function is allowed to deviate within given bounds. A simple search scheme is presented and it is shown that, by appropriate perturbation of the filter coefficients, one can dramatically reduce the number of adders required in the filter implementation. Using these approaches, on an average, less than one adder per coefficient is required, in contrast to a full-width multiplier. Hence, the presented methodologies are a useful compliment to the existing design approaches of high-performance and low-power digital filters for future mobile computing and communication systems. View full abstract»

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  • A bipartition-codec architecture to reduce power in pipelined circuits

    Page(s): 84 - 89
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    Proposes a new bipartition-codec architecture that may reduce the power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a finite-state machine. If the output of a pipelined circuit mainly transitions among just a few states, we can partition the combinational portion of a pipelined circuit into two blocks: the one that contains the few states of high activity is small, and the other (that contains the remainder of low activity) is large. Consequently, the state transitions are confined to the small block most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions; thus, the switching which propagates into the decoder is reduced considerably. We present experimental results on several MCNC benchmarks and obtain power savings of up to 63.7% by using our new architecture. View full abstract»

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  • AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths

    Page(s): 91 - 97
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    Describes AKORD, a transistor-level and mixed transistor/gate-level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post-placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD dynamically supports: (1) transistor folding without the usage of device libraries that contain variants of the same device; (2) device merging, including information about optimal transistor chain formation; and (3) well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest. View full abstract»

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  • Analytical approach to custom datapath design

    Page(s): 98 - 101
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    Addresses the problem of the layout design automation of a datapath cell. We present a novel approach to the transistor placement problem for custom datapath design and we demonstrate that it can be applied to practical designs. Our approach is based on an analytical model which employs a mixed integer linear programming (MILP) technique. The novelty and originality of the method is the efficient management of the complexity of the underlying mathematical model. Our prototype tool automatically handles transistor merging, folding and intra-cell component sharing. View full abstract»

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  • An integrated algorithm for combined placement and libraryless technology mapping

    Page(s): 102 - 105
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    This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state-space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits. View full abstract»

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  • Timing-driven partitioning for two-phase domino and mixed static/domino implementations

    Page(s): 107 - 110
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    Domino logic is a high-performance circuit configuration that is usually embedded in a static logic environment and tightly coupled with the clocking scheme. In this paper the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided In addition, an efficient static mapping algorithm is described. View full abstract»

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  • Implication graph based domino logic synthesis

    Page(s): 111 - 114
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    In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on an implication graph can reduce transistor counts by 25% and power delay product by 25% on average. View full abstract»

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  • Synthesis for multiple input wires replacement of a gate for wiring consideration

    Page(s): 115 - 118
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    The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper we propose two new transformations of replacing wires. One transformation simultaneously replaces multiple input wires of a gate by a new set of input wires and the other performs gate decomposition during the alternative wire process. To accomplish such complex transformations, we discuss some theoretical foundations for replacing multiple wires. Understanding how wires/gates can be replaced by other wires/gates allows us to speedup the process tremendously. View full abstract»

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  • Transient sensitivity computation for transistor level analysis and tuning

    Page(s): 120 - 123
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    This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that employ piecewise linear device models. This transient sensitivity capability is intended to be used in a simulation environment for transistor level analysis and tuning. Results demonstrate the efficiency and accuracy of the proposed techniques. Examples are also presented to illustrate how the transient sensitivity capability is used in timing characterization and circuit tuning. View full abstract»

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