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New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International

Date 16-19 June 2013

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Displaying Results 1 - 25 of 117
  • A fault tolerant NoC architecture based upon external router backup paths

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    As the scale of integration of digital circuits increases, there is a corresponding increase in the probability of permanent failures in NoCs. As a result, it is essential that NoCs have fault tolerance mechanisms in order to cope with this issue. In this article, we present a NoC architecture for a fault-tolerant multiprocessor chip based upon the use of backup paths which are external to the router, which allows maintaining communication between non-faulty network's routers. In the event of a permanent failure in a router, the control mechanism of backup paths is triggered in such a way that the faulty router is by-passed and the data is routed in a transparent way. Thus, data going through the faulty router from east to west and from north to south go all the way through to the final destination. The routing algorithm used in this version of the architecture uses a modified version of the XY routing algorithm. The results of performance evaluation show that the proposed architecture has a higher resiliency and provides lower latency than NoCs that make use of partially adaptive or stochastic algorithms. View full abstract»

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  • All-magnetic analog associative memory

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB) |  | HTML iconHTML  

    Associative memories and neurocomputing systems represent a massively parallel computing paradigm. Although extremely efficient for certain applications such as pattern recognition and image processing, such systems are not efficiently implemented using traditional CMOS design technology due to the required circuit complexity and corresponding power consumption to perform neural computations and represent programmable connections between artificial neurons. In this paper we propose to use newly-proposed mCell devices, which act as switchable non-volatile resistances, to implement an all-magnetic analog associative memory. We describe our building blocks for both artificial neurons and synapses using such magnetic devices. We verify the functionality of our proposed architecture using circuit simulation models of the mCell devices based on the first-order device physics. View full abstract»

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  • A 12-bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1091 KB) |  | HTML iconHTML  

    A low power successive approximation register ADC (SAR ADC) using a high performance integer-based split capacitor array combining with a mixed switching strategy is presented in this work. The split capacitor is chosen to be 2 times unit capacitance rather than the traditional non-integer value which is difficult to get. This array features high linearity, low area and power consumption. Besides, a mixed switching strategy combining the merged capacitor switching with monotonic switching is also used to save half of total capacitance. And a time domain comparator is used to achieve better offset performance. Implemented in a 0.18-μm CMOS technology, the proposed ADC is measured to have a 65.5 dB signal-to-noise-and-distortion ratios(SNDR) which leads to a 10.6 effective number of bits(ENOB) at 200KS/s sampling rate. Its power consumption is 1.49-μW and figure of merit (FOM) is only 4.87 fJ/c-s at a voltage supply of 0.9V. View full abstract»

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  • Designing globally-asynchronous-locally-system from multi-rate Simulink model

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (693 KB) |  | HTML iconHTML  

    Model-based design (MBD) tools such as HDL Coder from MathWorks are becoming increasingly popular among system designers aiming for fast-prototyping and design reuse. This paper discusses the performance issues related to the synchronous designs generated by HDL Coder for multi-rate systems, and proposes an alternative GALS-based design flow that can achieve high performance efficiency and high design modularity at the same time. Implementation results based on real-time radar signal processing algorithm demonstrate the performance advantage of the proposed GALS design style, which can also be traded for area when the performance requirements can be easily met. View full abstract»

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  • Nested hysteretic current-mode single-inductor multiple-output (SIMO) boosting buck converter

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (881 KB) |  | HTML iconHTML  

    Portable microsystems, which typically incorporate transceivers, analog/digital converters, microprocessors, and others, require several fast on-chip supplies to both function and save energy. Linear regulators are fast and compact, but also lossy, and although switched inductors are efficient, power inductors are bulky, which is why supplying several functions with one inductor is often an optimal compromise. Responding quickly to individual disruptions, however, is challenging when sharing one inductor with other loads, and bucking and boosting the battery voltage normally require more power switches. The 1.25-MHz single-inductor multiple-output (SIMO) converter presented here employs a buck stage to buck and boost 3.6 V to 0.8, 1.2, and 4.5 V and uses nested hysteretic current-mode control to respond within 1 μs to 20-mA load dumps across 0.8 and 1.2 V and 2 μs to 5-mA load dumps across 4.5 V. Simulations show that efficiency peaks at 91% 0/0 with a combined load of 45 mA. View full abstract»

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  • An efficient multispectral palmprint identification system using radial basis function

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (611 KB) |  | HTML iconHTML  

    Several studies for palmprint-based personal identification have focused on improving the performance of palmprint images captured under visible light. However, during the past few years, some researchers have considered multispectral images to improve the effect of these systems. Compared with color images, multispectral images provide additional information due to its variety of spectral bands. In this paper, we propose an efficient online personal identification system based on MultiSpectral Palmprint (MSP) using the Radial Basis Function (RBF) and two-dimensional Block based Discrete Cosine Transform (2D-BDCT). In this study, a segmented MSP is firstly divided into non-overlapping and equal-sized blocks, and then, applies the 2D-BDCT over each block. By using zigzag scan order (starting at the top-left) each transform block is reordered to produce the feature vector. Subsequently, RBF method is used for modeling and so for classifying the feature vectors. The proposed method is validated for their efficacy on the available PolyU MSP Database of 300 users. Our experimental results show the effectiveness and reliability of the proposed approach, which brings both high identification and accuracy rate. View full abstract»

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  • Wireless telemetry system for implantable cardiac monitoring in small animal subjects using pressure-volume sensors

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (933 KB) |  | HTML iconHTML  

    We present the discrete prototype version of our design of a wireless telemetry system architecture, which is suitable for custom IC implementation and intended to eventually retrieve blood pressure and volume (PV) data from small animal subjects (e.g., mice, rats). The architecture consists of four system level blocks that are stacked in 2.475cm3 volume and it weights 4.01g. The current prototype's size is well suited for commercial implementation inside medium sized animal subjects as, for instance, rabbits and larger rats. View full abstract»

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  • DAC waveform effects in CT incremental ΣΔ ADCs for biosensor applications

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (889 KB) |  | HTML iconHTML  

    Incremental sigma-delta (IΣΔ) analog-to-digital converters (ADCs), which are essentially ΣΔ ADCs with periodic resetting, are well suited for low-power low-speed biosensor applications. In recent years, the potential advantage in terms of power dissipation of continuous-time (CT) IΣΔ ADCs have been explored. This paper analyzes the impact of feedback digital-to-analog converters (DACs) on the performance of CT IΣΔ ADCs. Different feedback DAC schemes are firstly analyzed and then evaluated by employing them in a 3rd order single-bit CT IΣΔ ADC. Simulation results are discussed considering the trade-off between the timing error sensitivity and the power consumption, thereby offering a reference for selecting a power efficient feedback DAC scheme. View full abstract»

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  • Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    In this paper, an approach to the partitioning of parameterized 45-degree polygons into parameterized trapezoids by using horizontal cuts is proposed. In the process of partitioning a parameterized 45-degree polygon, the proposed approach invokes a mixed integer linear programming solver only once and can rapidly obtain results of comparing linear expressions. Compared with previous partitioning programs, the program implementing the proposed approach is very efficient and can achieve more than 100× speed-up while partitioning large parameterized polygons or parameterized polygons with complex constraints. The approach can be used as the basis to build trapezoidal corner stitching data structures for parameterized 45-degree layouts so that models of layout-induced parasitics can be generated automatically. View full abstract»

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  • A CMOS cyclic folding A/D converter with a new compact layout technique

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1811 KB) |  | HTML iconHTML  

    In this paper, a 9-bit 2MS/s CMOS cyclic folding A/D Converter(ADC) for a Battery Management System(BMS) is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 1mW at 3.3V. The occupied active die area is 10mm2. View full abstract»

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  • Efficient arithmetic logic gates using double-gate silicon nanowire FETs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    Silicon NanoWire (SiNW) based Field Effect Transistors (FETs) are promising candidates to extend Moore's law in the coming years. Recently, Double-Gate (DG) SiNWFETs have been demonstrated to allow on-line configurability of n-type and p-type device polarity through the second gate. Such feature enables novel compact realizations for XOR- and MAJ-based logic gates that are intensively used in arithmetic applications. In this paper, we present a complete design framework of DG-SiNWFETs technology for arithmetic logic. We characterize and validate compact arithmetic logic gates (XOR, MAJ, FA) using circuit level simulations. SiNW-based controllable polarity transistors at 22-nm technology node, first characterized at the physical level with Synopsys Sentaurus, enable a full-adder implementation about 3.8× faster than its CMOS FinFET 22-nm counterpart, according to HSPICE circuit simulations. Then, we study the application of these arithmetic gates in the automated synthesis of datapath circuits which are dominated by arithmetic operations. Experimental results show that datapath circuits synthesized in DG-SiNWFETs 22-nm technology are about 1.5× faster than in CMOS FinFET 22-nm technology while having practically the same area occupation. View full abstract»

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  • Standard CMOS voltage-mode QLUT using a clock boosting technique

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1053 KB) |  | HTML iconHTML  

    Interconnect has become preponderant in many aspects of digital circuit design, namely delay, power and area. This effect is particularly true for FPGAs, where interconnection is often the most limiting factor. Multiple-valued logic allows to reduce interconnections, within logic cells and between them, hence effectively mitigating the impact of interconnections. In this paper we propose a new look-up table structure based on a low-power high-speed quaternary voltage-mode device. Our quaternary implementation overcomes the drawbacks of previously proposed techniques by using a standard CMOS technology and a clock boosting technique to enhance speed without increasing consumption. Moreover, we present an ASIC prototype of a full adder based on the designed look-up table and experimental results are obtained and compared with simulation. The prototype is designed to work at 100 MHz and it consumes 128 μW. View full abstract»

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  • Demodulation of aggregated RF signals with a unique Rx chain

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (767 KB) |  | HTML iconHTML  

    In the next generation of the mobile radio systems, the information will be distributed on discontinuous frequency bands. To demodulate the RF signal, a possible architecture is to use a number of receivers Rx equal to that of the discontinuous RF frequency bands. This paper demonstrates that this operation can be made with a single receiver Rx. The method is based on the mixing of the RF signal with a local oscillator (LO) signal constituted by several Continuous Wave (CW) signals. The technique is studied theoretically and then applied to the case of RF signal constituted of two frequency bands. The CW frequencies of the LO signal are selected to convert both bands of the RF signal in Zero Intermediate Frequency (ZIF) and LOW Intermediate Frequency (LIF). View full abstract»

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  • Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1015 KB) |  | HTML iconHTML  

    The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due to the programmable interconnect overhead. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. We present a 3D design optimization methodology leveraged on Through Silicon Via (TSVs) to re-distribute the Tree interconnects into multiple stacked active layers using a tree-level horizontal break-point based on interconnect delay and to optimize the inter-layer heat dissipation. Nonetheless TSVs require a significant silicon area compared to planar interconnects and also bring critical challenges to the design of 3D ICs. In this paper we propose an architectural level interconnect and area optimization solution to minimize TSV count and programmable interconnects without compromising the FPGA performance. TSVs are also used very effectively to control the increase in inter-layer temperature of 3D ICs. We propose a TSV based 3D thermal optimization model for Tree-based FPGA. The experimental results from 3D Tree-based FPGA shows a 40% reduction of TSV count, 37% reduction in interconnect area and 28% reduction in power consumption. View full abstract»

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  • TI-ADCs SFDR requirement analysis

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    Impairments between ADCs are known to severely limit the resolution and bandwidth of time-interleaved (TI) architecture. This paper proposes a general framework describing simultaneously the gain, time-skew, bandwidth and offset mismatches. Statistical laws are analytically derived. They convert SFDR specifications into matching requirements and therefore provide key rules for TI-ADCs designers. View full abstract»

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  • An implementation and evaluation of Backward Euler algorithm to GPGPU power grid circuit simulation

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    This paper proposes a fast and accurate parallel transient simulator for power grid by Backward Euler method using GPU (Graphics Processing Unit). A new data structure CSG (Compressed Sparse for Grid structure) is proposed for the computational efficiency. The analysis flow is implemented by Jacobi relaxation with CSG. As the result, we have implemented a simulator whose speed is 74.0 times faster than CPU calculation. In addition, the accuracy is much higher than Forward Euler method, and comparable to HSPICE. View full abstract»

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  • Synchronous full-adder based on complementary resistive switching memory cells

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1014 KB) |  | HTML iconHTML  

    Emerging non-volatile memories (NVM) such as STT-MRAM and OxRRAM are under intense investigation by both academia and industries. They are based on resistive switching mechanisms and promise advantageous performances in terms of access speed, power consumption and endurance (i.e. >1012), surpassing mainstream flash memories. This paper presents a non-volatile full-adder design based on complementary resistive switching memory cells and validates it through two NVM technologies: STT-MRAM and OxRRAM on 40 nm node. This architecture allows low power consumption. Thanks to the nonvolatility and 3D integration of NVM, both standby power during “idle” state and data transfer power can be reduced. Using a low changing frequency can also control the switching power of NVM. The complementary cells and parallel data sensing enable fast computation and high reliability. View full abstract»

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  • Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (689 KB) |  | HTML iconHTML  

    This paper presents an analytical and comparative study on the design of the loop filter in frequency synthesizer Phase Locked Loops (PLLs). Loop filter design involves the selection of topology, type, order, poles ratio, noise contribution, and loop stability. The trade-offs involved in the design are elucidated and analyzed. The detailed analysis and simulation in this paper facilitate the selection of the loop filter that results in the optimum performance. Components selection through mathematical derivation and filter design tables is demonstrated. View full abstract»

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  • Emerging hybrid logic circuits based on non-volatile magnetic memories

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (906 KB) |  | HTML iconHTML  

    As the technology node shrinks down to 90 nm and below, high power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the increasing leakage currents and data traffic. Emerging non-volatile memories are under intense investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its quasi-infinite endurance, high speed and easy 3D integration at the back-end process of CMOS IC fabrication, Magnetic RAM (MRAM) is considered as one of the most promising candidates. A number of hybrid MRAM/CMOS logic circuits have been proposed and prototyped successfully in the last years. In this introduction paper for the invited special session at NEWCAS 2013, we present an overview and current status of these logic circuits and discuss their potential applications in the future. View full abstract»

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  • A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (786 KB) |  | HTML iconHTML  

    We propose a time-to-digital converter (TDC) that uses a Gm-C integrator to translate the time interval into voltage, and quantizes this voltage with a SAR-ADC. The proposed method is capable of achieving pico-second resolution, avoiding limitations in delay-chain-based TDCs, such as limited resolution to the buffer delay, mismatches, and voltage surge. Furthermore, taking the advantages of SAR-ADC, small area and low power consumption of voltage quantization are attainable. The chip was fabricated in 90nm CMOS. Its measured DNL and INL are -0.6/0.7 LSB and -1.1/2.3 LSB, respectively, with 1ps per LSB in a 9-bit range. View full abstract»

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  • Fully integrated Doherty power amplifier electromagnetically optimized in CMOS 65nm with constant PAE in backoff

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    A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. Electromagnetic models of each layout path were included in the optimization to dimension circuit components regarding parasitics of an accurate model. The method increased the PAE level in 6% through a constant 8.75 dB backoff range and increased in 2 dB the output power. The amplifier has an output power of 24 dBm, the first PAE peak is 26% and the second one 27%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce the number of inductances and to correctly balance active-loadpull effect. Comparisons were done between schematic, post-layout and electromagnetic simulation. View full abstract»

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  • Low complexity maximum likelihood estimation of time and frequency offset for DVB-T2

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB) |  | HTML iconHTML  

    The Second generation Terrestrial Digital Video Broadcasting (DVB-T2) standard provides a specific symbol, called PI symbol, in order to facilitate initial time and frequency synchronisation by identifying the correct start of the frame. Several schemes, exploiting this symbol, have been devised to perform this particular function. In this paper, a modified maximum likelihood estimation for the time and frequency offset is derived to significantly reduce the complexity of the maximum likelihood algorithm, without sacrificing performance. The proposed scheme is robust against continuous wave (CW) interference. Moreover, post FFT time synchronisation is no longer required. View full abstract»

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  • A 12-bit interpolated pipeline ADC using body voltage controlled amplifier

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1027 KB) |  | HTML iconHTML  

    This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback loop (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6 mW, almost half of the folded cascode (FC) amplifier satisfying 12-bit, 400 MS/s ADC operation. Moreover, the proposed amplifier secures 600 mV output swing, which is 1-VDS wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using proposed amplifier is demonstrated by 1P9M 90 nm process with 1.2 V supply voltage. The ADC achieves ENOB of about 10-bit at 300 MS/s and an FoM of 0.2 pJ/conv. when the frequency of the input signal is sufficiently low. View full abstract»

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  • A real-time power distribution based on load/generation forecasting for peak-shaving

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1802 KB) |  | HTML iconHTML  

    This paper proposes a real-time power distribution based on residential load/PV power generation forecasting for peak-shaving of electric power demand. This paper supposes a house with photovoltaic (PV) panel and battery, and proposes a power distribution method at household level to minimize a peak value of electric power demand. Experimental results show that the proposed method drastically cut the peak of electric power demand by up to 51%. View full abstract»

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  • A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write

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    The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and program state, respectively. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the sub-threshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present a ReRAM-based non-volatile flip-flop which is optimized for sub-VT operation. Writing to the ReRAM devices works with a CMOS-compatible supply voltage. Thanks to near-VT and sub-VT operation and as compared to the write energy, which depends on the ReRAM technology, the read consumes only 5.4% of the total read+write energy. Monte Carlo simulations accounting for parametric variations in both the MOS transistors and the ReRAM devices confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV, and a standard deviation of up to 5% of the nominal value of the ReRAM resistance. View full abstract»

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