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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

Date 5-7 June 2013

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  • [USB label]

    Publication Year: 2013, Page(s): 1
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  • [USB welcome]

    Publication Year: 2013, Page(s): 1
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  • Hub page

    Publication Year: 2013, Page(s): 1
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  • Session list

    Publication Year: 2013, Page(s): 1
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  • Table of contents

    Publication Year: 2013, Page(s):1 - 11
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  • Author index

    Publication Year: 2013, Page(s):1 - 6
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  • Detailed author index

    Publication Year: 2013, Page(s):1 - 36
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  • The end of indexes

    Publication Year: 2013, Page(s): 1
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  • About page

    Publication Year: 2013, Page(s): 1
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  • Frequently asked questions

    Publication Year: 2013, Page(s):1 - 6
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  • Message from the ASAP 2013 chairs

    Publication Year: 2013, Page(s):1 - 2
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  • Conference committee

    Publication Year: 2013, Page(s):1 - 3
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  • An application-aware approach to systems support for big data [Keynote address]

    Publication Year: 2013, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (46 KB)

    Summary form only given. Everyday 2.5 quintillion (2.5×1018, or 2.5 million trillion) bytes of data are created by people. This data comes from everywhere: from traditional scientific computing and on-line transactions, to popular social network and mobile applications. Data produced in the last two years alone amounts to 90% of the data in the world today! This phenomenal growth and ubiqui... View full abstract»

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  • Extreme scale computer architecture: Energy efficiency from the ground up [Keynote address]

    Publication Year: 2013, Page(s): 1
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    Summary form only given. As we move to higher levels of integration, it is clear that power and energy efficiency are the most formidable barriers. A chip built out of 1000 cores requires fundamentally rethinking the whole compute stack from the ground up for energy efficiency. Often, energy efficiency is in direct conflict with resilience. In this talk, I will describe some of the architecture te... View full abstract»

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  • From green computing to big-data learning: A kernel learning perspective [Keynote address]

    Publication Year: 2013, Page(s): 1
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    Summary form only given. The SVM learning model has been successfully applied to an enormously broad spectrum of application domains and has become a main stream of the modern machine learning technologies. Unfortunately, along with its success and popularity, there also raises a grave concern on it suitability for big data learning applications. For example, in some biomedical applications, the s... View full abstract»

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  • Wireless health: Challenges and opportunities

    Publication Year: 2013, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (39 KB)

    Summary form only given, as follows. Wireless Health brings to fruition many opportunities to continuously monitor human body with sensors placed on body or implanted in the body. These platforms will revolutionize many application domains including health care and wellness. They provide new avenues to continuously monitor individuals, whether it is intended to detect an early onset of a disease o... View full abstract»

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  • The tunnel vision syndrome: Massively delaying progress

    Publication Year: 2013, Page(s): 1
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    Summary form only given. Not only the multicore dilemma massively reduces programmer productivity and the progress of energy-efficient performance — a critical issue for the long term overall affordability of computing. Because of the Tunnel Vision Syndrome the solutions coming from a few isolated areas, are by far too slow and massively imperfect. Systolic arrays (SA) have been introduced ... View full abstract»

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  • Program

    Publication Year: 2013, Page(s):1 - 4
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  • Symbolic parallelization of loop programs for massively parallel processor arrays

    Publication Year: 2013, Page(s):1 - 9
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    In this paper, we present a first solution to the unsolved problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This problem arises for loop programs for which the iterations shall be optimally scheduled on a processor array of unknown size at compile-time. Still, we show that it is possible to derive parameterized latencyoptimal schedules staticall... View full abstract»

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  • Loop program mapping and compact code generation for programmable hardware accelerators

    Publication Year: 2013, Page(s):10 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    We present a novel design methodology for the mapping of nested loops onto programmable hardware accelerators. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) the underlying accelerator architectures consist of lightweight, tightly-coupled, and programmable processor arrays, which can exploit both... View full abstract»

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  • Aspect driven compilation for dataflow designs

    Publication Year: 2013, Page(s):18 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (181 KB) | HTML iconHTML

    This paper proposes a novel hardware compilation approach targeting dataflow designs. This approach is based on aspect-oriented programming to decouple design development from design optimisation, thus improving portability and developer productivity while enabling automated exploration of design trade-offs to enhance performance. We introduce FAST, a language for specifying dataflow designs that ... View full abstract»

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  • Enabling development of OpenCL applications on FPGA platforms

    Publication Year: 2013, Page(s):26 - 30
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB) | HTML iconHTML

    High-level FPGA synthesis tools aim to increase the productivity of FPGAs and to adopt them among software developers and domain experts. OpenCL is a specification introduced for parallel programming across heterogeneous platforms. In this paper, an automated compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is reported. The flow use... View full abstract»

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  • Modelling communication overhead for accessing local memories in hardware accelerators

    Publication Year: 2013, Page(s):31 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    Local memories increase the efficiency of hardware accelerators by enabling fast accesses to frequently used data. In addition, the access latencies of local memories are deterministic which allows for more accurate evaluation of the system performance during design exploration. We have previously proposed local memories with an un-cached memory slave interface that permits program running on the ... View full abstract»

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  • Cache partitioning and scheduling for energy optimization of real-time MPSoCs

    Publication Year: 2013, Page(s):35 - 41
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    Cache partitioning is a promising technique to reduce energy consumption of the cache subsystem for MPSoCs. Currently, most existing techniques focus primarily on static partition on core level. In this paper, we present a task-level approach and show that it outperforms core-level strategies. By taking the interference patterns of individual tasks into account, our approach generates optimal task... View full abstract»

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  • Accelerating HAC estimation for multivariate time series

    Publication Year: 2013, Page(s):42 - 49
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    Heteroskedasticity and autocorrelation consistent (HAC) covariance matrix estimation, or HAC estimation in short, is one of the most important techniques in time series analysis and forecasting. It serves as a powerful analytical tool for hypothesis testing and model verification. However, HAC estimation for long and high-dimensional time series is computationally expensive. This paper describes a... View full abstract»

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