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Proceedings of the 2013 Electronic System Level Synthesis Conference (ESLsyn)

May 31 2013-June 1 2013

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Displaying Results 1 - 19 of 19
  • [Front-cover]

    Publication Year: 2013, Page(s): c1
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  • [Title page]

    Publication Year: 2013, Page(s): 1
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  • Table of contents

    Publication Year: 2013, Page(s): 1
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  • Welcome

    Publication Year: 2013, Page(s):1 - 5
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  • Session 1: High-level synthesis

    Publication Year: 2013, Page(s): 1
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  • Partial controller retiming in high-level synthesis

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (142 KB) | HTML iconHTML

    Various optimization techniques of high-level synthesis (HLS) have been studied for improving clock frequency. However, they focus only on the datapath and cannot handle the controller delay even though most critical paths lie across the controller and datapath (i.e., from state registers in the controller to storage units in the datapath) and the controller delay occupies the non-negligible porti... View full abstract»

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  • System level synthesis of dataflow programs: HEVC decoder case study

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB)

    While dealing with increasing complexity of signal processing algorithms, the primary motivation for the development of High-Level Synthesis (HLS) tools for the automatic generation of Register Transfer Level (RTL) description from high-level description language is the reduction of time-to-market. However, most existing HLS tools operate at the component level, thus the entire system is not taken... View full abstract»

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  • Synthesis and optimization of high-level stream programs

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (127 KB) | HTML iconHTML

    In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synthesis available for a large class of programs, and methodology and tool support providing analysis and guidance to improve and optimize an initi... View full abstract»

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  • Session 2: Work-in-Progress

    Publication Year: 2013, Page(s): 1
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  • Automatic partitioning of behavioral descriptions for high-level synthesis with multiple internal throughputs

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    This works presents a method for automatically partitioning single process behavioral descriptions (ANSI-C or SystemC) into separate processes under a given global throughput constraint. The proposed method identifies parts in the process with different internal Data Initiation Intervals (DIIs) and partitions it into sub-processes that can in turn be optimized independently. Experimental results s... View full abstract»

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  • From multicore simulation to hardware synthesis using transactions

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB) | HTML iconHTML

    With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become necessary. This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to achieve an automatic high-level synthesis fl... View full abstract»

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  • Efficient preemption of loops for dynamic HW/SW partitioning on configurable systems on chip

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB) | HTML iconHTML

    With the advance of high-level synthesis methodologies it has become possible to transform software tasks, typically running on a processor, to hardware tasks running on an FPGA device. Furthermore, dynamic reconfiguration techniques allow dynamic scheduling of hardware tasks on an FPGA area at runtime. The combination of these techniques allows dynamic scheduling across the hardware-software boun... View full abstract»

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  • Session 3: System-level modelling & synthesis

    Publication Year: 2013, Page(s): 1
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  • Scalable high quality hierarchical scheduling

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    List scheduling is well known for its implementation simplicity and O(N2) scalability, but not for result quality. The Ant-Colony scheduling algorithm, imitating the cooperative behaviors of ants, does generate high quality results, but like any stochastic search, has potentially long run times to assure high result quality. This paper presents a hierarchical scheduling algorithm using ... View full abstract»

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  • Multi-core cache hierarchy modeling for host-compiled performance simulation

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    The need for early software evaluation has increased interest in host-compiled or source-level simulation techniques. For accurate real-time performance evaluation, dynamic cache effects have to be considered in this process. However, in the context of coarse-grained simulation, fast yet accurate modeling of complex multi-core cache hierarchies poses several challenges. In this paper, we present a... View full abstract»

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  • Pre- and post-scheduling memory allocation strategies on MPSoCs

    Publication Year: 2013, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB) | HTML iconHTML

    This paper introduces and assesses a new method to allocate memory for applications implemented on a shared memory Multiprocessor System-on-Chip (MPSoC). This method first consists of deriving, from a Synchronous Dataflow (SDF) algorithm description, a Memory Exclusion Graph (MEG) that models all the memory objects of the application and their allocation constraints. Based on the MEG, memory alloc... View full abstract»

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  • Invited papers

    Publication Year: 2013, Page(s): 1
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  • Precision timed infrastructure: Design challenges

    Publication Year: 2013, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (605 KB) | HTML iconHTML

    In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening consequences. Although many modern modeling languages for CPS include the notion of t... View full abstract»

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  • System synthesis from UML/MARTE models: The PHARAON approach

    Publication Year: 2013, Page(s):1 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (395 KB) | HTML iconHTML

    Model-Driven Engineering (MDE) based on UML is a mature methodology for software development. However, its application to HW/SW embedded system specification and design requires specific features not covered by the language. For this reason, the MARTE profile for Real-Time and Embedded systems was defined. It has proven to be powerful enough to support holistic system modeling under different view... View full abstract»

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