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Computer Arithmetic (ARITH), 2013 21st IEEE Symposium on

Date 7-10 April 2013

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Displaying Results 1 - 25 of 42
  • [Front cover]

    Publication Year: 2013 , Page(s): C4
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  • [Title page i]

    Publication Year: 2013 , Page(s): i
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  • [Title page iii]

    Publication Year: 2013 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2013 , Page(s): iv
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  • Table of contents

    Publication Year: 2013 , Page(s): v - vii
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  • Foreword

    Publication Year: 2013 , Page(s): viii
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  • Dedication: In memory of Luigi Ciminiera 1954-2012 [includes "In memory of Luigi Dadda 1923-2012"]

    Publication Year: 2013 , Page(s): ix - xi
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  • Steering Committee

    Publication Year: 2013 , Page(s): xii
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  • Symposium Committee

    Publication Year: 2013 , Page(s): xiii
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  • Program Committee

    Publication Year: 2013 , Page(s): xiv
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  • Additonal reviewers

    Publication Year: 2013 , Page(s): xv
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  • Corporate sponsors

    Publication Year: 2013 , Page(s): xvi
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  • High-precision computation: Applications and challenges [Keynote I]

    Publication Year: 2013 , Page(s): 3
    Request Permissions | Click to expandAbstract | PDF file iconPDF (116 KB)  

    Summary form only given, as follows. High-precision floating-point arithmetic software, ranging from "double-double" or "quad" precision to arbitrarily high-precision (hundreds or thousands of digits), has been available for years. Such facilities are standard features of Mathematica and Maple, and software packages such as MPFR, QD and ARPREC are available on the Internet. Some of these packages ... View full abstract»

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  • The Floating-Point Unit of the Jaguar x86 Core

    Publication Year: 2013 , Page(s): 7 - 16
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    The AMD Jaguar x86 core uses a fully-synthesized, 128-bit native floating-point unit (FPU) built as a co-processor model. The Jaguar FPU supports several x86 ISA extensions, including x87, MMX, SSE1 through SSE4.2, AES, CLMUL, AVX, and F16C instruction sets. The front end of the unit decodes two complex operations per cycle and uses a dedicated renamer (RN), free list (FL), and retire queue (RQ) f... View full abstract»

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  • Split-Path Fused Floating Point Multiply Accumulate (FPMAC)

    Publication Year: 2013 , Page(s): 17 - 24
    Request Permissions | Click to expandAbstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    Floating point multiply-accumulate (FPMAC) unitis the backbone of modern processors and is a key circuit determining the frequency, power and area of microprocessors. FPMAC unit is used extensively in contemporary client microprocessors, further proliferated with ISA support for instructions like AVX and SSE and also extensively used in server processors employed for engineering and scientific app... View full abstract»

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  • FPU Generator for Design Space Exploration

    Publication Year: 2013 , Page(s): 25 - 34
    Request Permissions | Click to expandAbstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    FPUs have been a topic of research for almost a century, leading to thousands of papers and books. Each advance focuses on the virtues of some specific new technique. This paper compares the energy efficiency of both throughput-optimized and latency-sensitive designs, each employing an array of optimization techniques, through a fair "apples to apples" methodology. This comparison required us to b... View full abstract»

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  • Special session: Managing computation, precision, accuracy and performance on exascale systems [breaker page]

    Publication Year: 2013 , Page(s): 37
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  • Improved Architectures for a Floating-Point Fused Dot Product Unit

    Publication Year: 2013 , Page(s): 41 - 48
    Cited by:  Papers (1)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    This paper presents improved architectures for a floating-point fused two-term dot product unit. The floating-point fused dot product unit is useful for a wide variety of digital signal processing (DSP) applications including complex multiplication and fast Fourier transform (FFT) and discrete cosine transform (DCT) butterfly operations. In order to improve the performance, a new alignment scheme,... View full abstract»

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  • Floating Point Architecture Extensions for Optimized Matrix Factorization

    Publication Year: 2013 , Page(s): 49 - 58
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (407 KB) |  | HTML iconHTML  

    This paper examines the mapping of algorithms encountered when solving dense linear systems and linear least-squares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations. As part of the study, we expose the benefits of redesigning floating point units and their surrounding data-paths to support these complicated op... View full abstract»

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  • A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers

    Publication Year: 2013 , Page(s): 59 - 66
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (617 KB) |  | HTML iconHTML  

    Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both value and address of the maximum element with... View full abstract»

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  • A Non-Linear/Linear Instruction Set Extension for Lightweight Ciphers

    Publication Year: 2013 , Page(s): 67 - 75
    Request Permissions | Click to expandAbstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    Modern cryptography today is substantially involved with securing lightweight (and pervasive) devices. For this purpose, several lightweight cryptographic algorithms have already been proposed. Up to now, the literature has focused on hardware-efficiency while lightweight with respect to software has barely been addressed. However, a large percentage of lightweight ciphers will be implemented on e... View full abstract»

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  • The Antikythera Mechanism and the early history of mechanical computing

    Publication Year: 2013 , Page(s): 79
    Request Permissions | Click to expandAbstract | PDF file iconPDF (101 KB)  

    Summary form only given, as follows. Doing arithmetic has probably been necessary since civilization began. We now know that the ancient Greeks were able to make mechanical devices capable of calculation. The Antikythera Mechanism is an extraordinary device containing over thirty gear wheels dating from the 1st century BC, and is an order of magnitude more complicated than any surviving mechanism ... View full abstract»

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  • On the Componentwise Accuracy of Complex Floating-Point Division with an FMA

    Publication Year: 2013 , Page(s): 83 - 90
    Request Permissions | Click to expandAbstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    This paper deals with the accuracy of complex division in radix-two floating-point arithmetic. Assuming that a fused multiply-add (FMA) instruction is available and that no underflow/overflow occurs, we study how to ensure high relative accuracy in the component wise sense. Since this essentially reduces to evaluating accurately three expressions of the form ac+bd, an obvious approach would be to ... View full abstract»

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  • How to Compute the Area of a Triangle: A Formal Revisit

    Publication Year: 2013 , Page(s): 91 - 98
    Request Permissions | Click to expandAbstract | PDF file iconPDF (723 KB) |  | HTML iconHTML  

    Mathematical values are usually computed using well-known mathematical formulas without thinking about their accuracy, which may turn awful with particular instances. This is the case for the computation of the area of a triangle. When the triangle is needle-like, the common formula has a very poor accuracy. Kahan proposed in 1986 an algorithm he claimed correct within a few ulps. Goldberg took ov... View full abstract»

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  • SIPE: Small Integer Plus Exponent

    Publication Year: 2013 , Page(s): 99 - 106
    Request Permissions | Click to expandAbstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    SIPE (Small Integer Plus Exponent) is a mini-library in the form of a C header file, to perform floating-point computations in very low precisions with correct rounding to nearest in radix 2. The goal of such a tool is to do proofs of algorithms/properties or computations of tight error bounds in these precisions by exhaustive tests, in order to try to generalize them to higher precisions. The cur... View full abstract»

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