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Test Conference, 1999. Proceedings. International

Date 30-30 Sept. 1999

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  • International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)

    Publication Year: 1999
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    Freely Available from IEEE
  • Panel: Increasing test coverage in a VLSI desgin course

    Publication Year: 1999, Page(s): 1131
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  • Position Statement: Increasing Test Coverage in a VLSI Design Course

    Publication Year: 1999, Page(s): 1132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (77 KB)

    It is argued that test and verification (validation) have a lot in common. The test problem is a (small) subset I of the verification problem. The concept of justification is useful for both problems. Practical formal Bbolean equivalence checking tools draw heavily on algorithms from the test field. ATPG techniqu~s are beginning to be applied to other verification problems. A VLSI design course sh... View full abstract»

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  • Increasing Test Coverage in a VLSI Design Course

    Publication Year: 1999, Page(s): 1133
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    VLSI Designers know so little about testing that the large, multi-national corporations frequently higher test experts to advise their designers on test problems. The companies even pay a higher salary to the testing experts than to their VLSI Designers. The author's position is that three lectures in every VLSI Design course should be devoted to test. The first lecture would touch briefly on Test... View full abstract»

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  • VLSI design 101 - The test module

    Publication Year: 1999, Page(s): 1134
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB)

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  • Increasing test coverage in a VLSI design course

    Publication Year: 1999, Page(s): 1135
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (111 KB)

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  • Panel Statement: Increasing test coverage in a VLSI design course

    Publication Year: 1999, Page(s): 1136
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  • Author index

    Publication Year: 1999, Page(s):1156 - 1157
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  • Test process optimization: closing the gap in the defect spectrum

    Publication Year: 1999, Page(s):124 - 129
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    This paper describes our methodology of tuning the test process of the Motorola Operations and Maintenance Center product to systematically reduce field defects. The benefits include improved test cases, reduced defects and the availability of up to date field data for feature verification View full abstract»

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  • High level ATPG is important and is on its way!

    Publication Year: 1999, Page(s):1115 - 1116
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    ATPG is about test functionality that leads to test patterns to determine the quality of a chip. Traditionally, this technology has been available at the gate level and this paper describes the need to move higher. High Level is defined as any level in the abstraction chain that is above gates. DRC and DFT technology have already moved to higher levels of abstraction. If necessity is the mother of... View full abstract»

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  • Defect detection using power supply transient signal analysis

    Publication Year: 1999, Page(s):67 - 76
    Cited by:  Papers (38)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. The power supply transient signals of an 8-bit multiplier are analyzed using both hardware and simulation experiments. The small signal variations generated at these test points are analyzed in both the time and frequency domain. A simple statistical procedure i... View full abstract»

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  • High-level ATPG: a real topic or an academic amusement?

    Publication Year: 1999, Page(s): 1118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

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  • Testability evaluation of sequential designs incorporating the multi-mode scannable memory element

    Publication Year: 1999, Page(s):286 - 293
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on ... View full abstract»

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  • Switch-level delay test

    Publication Year: 1999, Page(s):171 - 180
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    Gate-level models are usually used to generate tests for circuits containing non-primitive CMOS gates. It is shown that tests generated using these models and classical conditions for robust path delay testing can fail to detect delay faults in such circuits. A new delay-independent, switch-level delay test methodology, called τ-robust testing, is proposed that defines new entities called targ... View full abstract»

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  • Scan Insertion at the Behavioral Level

    Publication Year: 1999, Page(s): 1126
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  • Limited access testing of analog circuits: handling tolerances

    Publication Year: 1999, Page(s):577 - 586
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    This paper deals with in-circuit testing of analog circuits that have limited access. A new method to account for tolerances on device values is presented, with results illustrating good performance in a production test environment View full abstract»

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  • At-speed structural test

    Publication Year: 1999, Page(s):795 - 800
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Structural test can address only stuck-at faults unless some dynamic capability is included. The dynamic capability required starts with two-vector launch-capture delay tests, but evolves rapidly to include gated clock bursts, perhaps synchronized with primary I/O's. This implies an at-speed structural test architecture which incorporates many of the capabilities of functional test systems View full abstract»

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  • PC manufacturing test in a high volume environment

    Publication Year: 1999, Page(s):698 - 704
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper will introduce the reader to a wide range of issues related to choosing and implementing the proper manufacturing test philosophy for a given situation. The issues which need to be understood when formulating a manufacturing test philosophy are the manufacturing environment, the customer's requirements, the fault spectrum of interest, and the relative strengths and weaknesses of differe... View full abstract»

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  • Test support processors for enhanced testability of high performance circuits

    Publication Year: 1999, Page(s):801 - 809
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1156 KB)

    A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to incl... View full abstract»

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  • Accurate path delay fault coverage is feasible

    Publication Year: 1999, Page(s):201 - 210
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    We examine the problem of determining the exact number of path delay faults that a given set of p pairs of patterns detects in a combinational circuit consisting of I lines. Several fault coverage pessimistic heuristics and exact algorithms with worst case exponential behavior have been recently presented with trade-offs between the quality of fault coverage and the time performance. None of the e... View full abstract»

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  • Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks

    Publication Year: 1999, Page(s): 1128
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  • Expediting ramp-to-volume production

    Publication Year: 1999, Page(s):103 - 112
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1672 KB)

    High levels of integration have complicated the entire IC manufacturing process. Crucial steps such as ramp to volume production and yield improvement techniques are being challenged. In this paper, a diagnostic system that has been developed and deployed into a production environment is presented. Experiments conducted demonstrating the value of the diagnostic tool and its limitations are present... View full abstract»

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  • Clustering based techniques for IDDQ testing

    Publication Year: 1999, Page(s):730 - 737
    Cited by:  Papers (27)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    A new technique for evaluating IDDQ data using a clustering based approach is presented. While prevailing IDDQ test techniques rely on a fixed threshold or the current signature of an IC, the proposed technique relies on abnormalities of the IDDQ distribution of a device with respect to other devices in the test set. Results of applying this technique to data colle... View full abstract»

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  • Resistive bridge fault modeling, simulation and test generation

    Publication Year: 1999, Page(s):596 - 605
    Cited by:  Papers (36)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    In this work1 we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the first resistive bridging fault ATPG, which attempts to detect ... View full abstract»

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  • Finite state machine synthesis with concurrent error detection

    Publication Year: 1999, Page(s):672 - 679
    Cited by:  Papers (36)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while... View full abstract»

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