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Date 10-12 Dec. 2012

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Displaying Results 1 - 25 of 101
  • Preface

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    Freely Available from IEEE
  • [Copyright notice]

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    Freely Available from IEEE
  • IEEE CPMT symposium Japan 2012 committee members

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    Freely Available from IEEE
  • Plenary speakers

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    Provides an abstract for each of the planary presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Program session

    Page(s): 1 - 18
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  • High-stability 25 Gb/s optical transceiver module with flexible polymer wave guide for optical interconnection

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    A high-stability and high-speed optical transceiver module for a chip-to-chip optical interconnection has been developed. The stability of optical power output is provided by optimizing the packaging structure snd thus reducing deformation of the module resulting from the bimetallic effect. (Degradation of optical coupling efficiency is reduced to 0.15 dB by limiting variations in temperature to a level between 25 and 75 deg C). High-speed(25 Gb/s) transmission is obtained by high transmitting rate devices and low-loss electrical wiring. View full abstract»

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  • A 25-Gbit/s high-speed optical-electrical printed circuit board for chip-to-chip optical interconnections

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    A high-speed opto-electronic printed circuit board (OEPCB) composed of a polymer waveguide and an optical module is conceptually proposed and prototyped. The fabricated OEPCB prototype provides highly efficient optical coupling characteristics (> -1 dB) and large optical-coupling tolerance (> +/-15 μm). It demonstrated 25-Gbit/s high-speed optical-signal transmission through a 10-cm-long multi-mode polymer waveguide. This performance result indicates that the OEPCB is suitable for next-generation high-speed and high-density chip-to-chip optical interconnection. View full abstract»

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  • Integrated package for 100G ethernet optical transmitter

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    We have succeeded in demonstrating the reconciliation of low current swing operation and high-performance electrical transmission for electro-absorption modulators (EAM) with high impedance termination and the filter (capacitor - inductor - capacitor) for the integrated package of 100 Gb/s Ethernet. Reducing operating current of 15% and clear eye-openings of an optical modulated waveform with the mask margin of 47% is achieved. View full abstract»

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  • Graded-index core polymer optical waveguide for high-speed and high-density on-board interconnects

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    We theoretically and experimentally demonstrate that graded-index (GI) core polymer optical waveguides are a promising component realizing high-speed and high-density on-board interconnects. As a fabrication method of the GI circular core polymer optical waveguides, we introduce the Mosquito method, in which we utilize a micro dispenser. By the Mosquito method, GI circular core polymer parallel optical waveguides with low-loss and low inter-channel crosstalk are fabricated successfully without using any types of photo mask. We also theoretically show that the GI-core polymer waveguides enable remarkably low loss waveguide circuits involving waveguide crossings in a mono layer. Although the Mosquito method is not suitable for the crossed waveguide fabrication, we show an alternative technique to realize the low loss GI-core crossed waveguide: the Photo-addressing method. View full abstract»

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  • Improvement of polynorbornene waveguide based O/E module performance with microlens structure

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1253 KB) |  | HTML iconHTML  

    The Optoelectronic (O/E) module with polymer waveguides is one of necessary items in order to realize optical interconnection technology. Generally, the optical coupling loss of O/E modules results from the gap between polymer waveguides and O/E devices mounted on electrical substrate. Reduction of the optical coupling loss is an important challenge because the coupling loss is contributory to increment of power consumption of O/E modules. In order to decrease the optical coupling loss, we propose polymer waveguides with lens structure for O/E module and its fabrication process. We report that optical loss was less than 3dB with lens structure. View full abstract»

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  • Light-induced self-written waveguide for optoelectronic integration devices

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB) |  | HTML iconHTML  

    We show the feasibility of optical interconnection waveguides formed by self-trapping effect with 0.85μm light irradiation into photopolymer. Self-written waveguides as extensions of both a single-mode fiber and a VCSEL chip were demonstrated. These technologies are useful for integration of chip-scale photonic device. View full abstract»

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  • Analysis of inter-channel crosstalk in multi-mode parallel optical waveguide using Beam Propagation Method

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (869 KB) |  | HTML iconHTML  

    We theoretically analyze the origin of inter-channel crosstalk in high-density multimode parallel optical waveguides for on-board interconnects using the Beam Propagation Method. In this paper, we demonstrate that inter-channel crosstalk due to mode coupling is very low in waveguides with GI-type circular cores because the propagation constants of the modes are discrete. Additionaly, it is also found that the waveguides with GI-type circular cores is sensitive to the optical confinment in the cladding: low power cladding modes largely decreases the mode conversion. View full abstract»

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  • Low-temperature bonding of laser diode chips using atmospheric-pressure plasma activation of flat topped Au stud bumps with smooth surfaces

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    Surface activation by atmospheric-pressure plasma has been used for low-temperature bonding of laser diode (LD) chips. Coined Au stud bumps with smooth surfaces (Ra: 1.3 nm) and Au thin film electrodes (Ra: 2.1 nm) of LD chips were activated by Ar+O2 or Ar+H2 atmospheric-pressure plasma for 30 s and bonded in ambient air at low-temperature (25-150°C). Bonding strength was high enough to exceed the strength requirement of MIL-STD-883F, method 2019 (×2). The measured results of light-current-voltage (L-I-V) characteristics of the LD chips indicated no degradation after bonding. View full abstract»

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  • Low temperature Cu-Cu direct bonding for 3D-IC by using fine crystal layer

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (815 KB) |  | HTML iconHTML  

    In this paper, we report a method of low temperature solid diffusion bonding. To investigate bondability of solid diffusion, we examined the effect of bump metals and bump planarization methods. Cu and Au bump were used for bump metals and CMP and ultra-precision cutting were used for bump planarization methods. We found that fine crystal layer could be formed on only cut Cu and Au bumps, and especially cut Cu bumps had a thick fine crystal layer on the surface. The layer on cut Cu bump was found to be easily to recrystallize at low temperature condition of 150 degree C. Moreover, the bonding interface of cut Cu bump disappeared at 200 degree C for 30 min, which means solid diffusion across the interface was realized with the contribution of fine crystal layer. In addition, for Cu-Cu direct bonding, formic acid treatment before bonding is effective because formic acid can react at low temperature without destroying fine crystal layer. That led to achieve high bonding strength between cut Cu bumps. View full abstract»

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  • Room temperature microjoining of qVGA class area-bump array using cone bump

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (349 KB) |  | HTML iconHTML  

    We show that room temperature microjoining a 332 × 268 array of bumps can be realized by using ultrasonic bonding of cone-shaped microbump. 20 μm-pitch area array of cone-shaped Au bump was fabricated on a Si wafer by using a photolithography and electroplating. A flat planar electrode made of electoplated Au was used as the counter electrode. Ultrasonic bonding was carried out at room temperature in ambient air. Electrical connection test shows all bump connections with low resistance have been achieved. View full abstract»

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  • Cu wire bonding knows no limit - 28 nm is qualified

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    Over the course of the last five years, fine pitch Cu wire bonding has gained a very large market share in the wire bond packaging market driven primarily by very high Au commodity prices. Virtually all IDMs and OSATs do offer Cu wire bond products. In ASE the penetration rate is reaching 60% or more than 9.5 billion units in shipment to date. The reliability has reached levels which equate to more than 6X of typical JEDEC package reliability testing protocols, and now, automotive as well as networking customers are ready to accept Cu wire bonded products for their applications. Current shipments do include 40 and 45 nm wafer technology and the question is arising how far can Cu wire bonding go? The ASE Cu wire bonding roadmap will be presented which aims at sustaining wire bonding in Cu to at least the 20 nm node. Qualification data will be presented for the 28 nm node based on collaboration with wafer fabs. Customer die qualifications are in progress. View full abstract»

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  • Impact test performance of Zn-based die-attach joints for power devices

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    Fracture behavior under high speed deformation of the high temperature solder joints with Pb-free Zn-Sn and commercial Pb-Sn alloys bonded on different surface finishes was studied by ball impact test (BIT) method. All in all, Zn-Sn joints exhibited greater impact strength but inferior impact toughness than Pb-Sn joints. This can be ascribed to the high hardness of Zn-Sn solders resulting in partial or overall interfacial fracturing. In contrast, the joints with soft Pb-Sn solders all showed a ductile fracture feature. It can be suggested that for the joints revealing brittle fracturing the impact toughness increased with the plastic ability of interfacial intermetallic compounds (IMCs), while those showing ductile fracture mode, the impact energy deteriorated with a hardened solder matrix resulting from substrate dissolution. View full abstract»

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  • Productivity improvement of copper pillar flip-chip package by pre-applied materials and press machine

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (979 KB) |  | HTML iconHTML  

    In this report, authors describe improvement effort of fine pitch flip-chip interconnection based on pre-applied material process. For evaluation, IC with copper pillar bumps (50 μm pitch) and organic boards (FR-5) have been used. NCF and B-stage material have been used as pre-applied connecting material. As a result, we have developed temporary alignment and subsequent batch bonding process to improve productivity. View full abstract»

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  • Joint reliability study of solder capped metal pillar bump interconnections on an organic substrate

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    Flip chip technology is widely used on the electronic packaging, and the market forces drive toward finer pitch interconnection. Cu pillar bump structure is a currently trend of the fine pitch flip chip package with less than 100μm bump pitch. But there is a solder volume limitation on solder capped Cu pillar bump structure. In addition, Cu may easily react with Sn-based solder into intermetallic compounds (IMCs). So it may be difficult for much finer pitch application with the structure. In this paper, we studied the fine pitch (50μm) flip chip interconnections with various bump structures and the die thickness. The 3-types of solder capped metal (Cu, Cu-Ni and Ni) pillar bumps and the 3-different die thickness (100μm, 300μm and 725μm) were evaluated. Finite Element Method (FEM) simulation was performed to analyze the thermal mechanical stress on the solder joint and on the root of metal pillar first. The result showed that the stress on the root of pillar on Ni pillar bump was higher than that of Cu pillar bump, and the stress on solder joint and the root of pillar was reduced by thinning the die thickness. To verify these results, the initial solder joints were observed using an optical microscope and a Scanning Electron Microscope (SEM). The IMC phases, the IMC growth and the interconnect microstructures were compared. After these observations, a thermal cycling test (Condition : -55°C/+125°C) was performed, then the lifetime was compared between Cu pillar bump and Ni pillar bump. In the study, we obtained good reliability data on both pillars, but the lifetime of Cu pillar bumps was 1.5 times better than that of Ni pillar bump with the same structure. In addition, the electro-migration (EM) test was performed to investigate the EM behavior of microjoints on Cu pillar bump and Ni pillar bump. In the study, there is no significant difference on the electrical resistance variation until 2,000hrs. View full abstract»

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  • Effect of preformed Cu-Sn IMC layer on electromigration reliability of solder capped Cu pillar bump interconnection on an organic substrate

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    The electromigration behavior of 80μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. In 2011, the EM tests were performed on 80μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7-10 kA/cm2 at 125-170°C. The Cu pillar height was 45μm and the solder height was 25μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atom dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2,000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10-50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5μm is effecti- e in reducing Cu dissolution in the joints. View full abstract»

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  • Fast life-time assessment of LED luminaries

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    The life-time assessment is becoming one of the major concerns for LED industry. It is highly requested to develop an effective and fast life-time qualification method to support and drive LED industry. In this paper, firstly an overview of the life-time assessment methods for LED products is conducted. A comparison has been made among the methods. Traditional constant stress accelerated test (CSAT) requires long test duration, with complication to select stress level, large sample size, high test cost and so on. The step stress accelerated test (SSAT) method has several advantages, such as suitable for long life field, short test time and few sample size, showing the potential for application to the reliability testing for LED products. Secondly, SSAT study was conducted on LED module and LED products. A design of experiments was performed based our preliminary SSAT results. Then a series of tests have been carried out. The effective accelerated degradation paths demonstrated that a fast life-time qualification procedure could be developed with step stress testing. Based on the test results, a step stress based fast life-time assessment approach is proposed for LED Products. View full abstract»

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  • Solid-state bonding using metallic cone layer for interconnection

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1603 KB) |  | HTML iconHTML  

    This paper describes the feasibility of using metallic cone layer in solid-state bonding with Sn-based solder. At temperature below the melting point of Sn, both Ni cones and Cu cones were found successful in forming robust joints with good bonding strength and compact interfaces. This method is also compatible with high-density micro bump interconnecting. Studies have also been carried out in combination with surface activation bonding. Mechanical insertion and controllable interfacial reactions functioning as key factors for realization of the bonding method were emphasized through theoretical study. This bonding method is expected to be potential for the applications in 3D integration. View full abstract»

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  • Ni barrier for tin whisker mitigation

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    In the present work, a close-to-product investigation was conducted in evaluating tin whisker growth on electroplated matte Sn films. The matte Sn films were deposited on Cu leadframes (C194). Electroplating Ni film was used as a barrier between the Sn film and the substrate. The experimental results revealed that Ni barrier could completely restrain the tin whisker growth after 8,000 hours storage at 55°C/85%RH. However, it was found that cracks often formed from the surface during forming process, reflow process and even storage under thermal/humidity condition. Crack formation and corresponding stresses in different processes were investigated. The thicker Ni barrier could induce considerable mechanical damage to the matte Sn films of the IC leads. It was found that thinner Ni barrier layer could withstand the forming stress, thermal mismatch stress and IMC-induced stress without causing cracks in the matte Sn films and thus did not promote Sn whisker growth. View full abstract»

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  • Heterogeneous integration of MEMS sensor array and CMOS readout IC with Through Silicon Via interconnects

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1572 KB) |  | HTML iconHTML  

    Through Silicon Via (TSV) forms electrical feedthrough and makes it possible to vertically stack chips with various functions which including logic, memory, analog and MEMS etc. This paper presents a TSV 3D- heterogeneous integration structure of MEMS sensor array with CMOS readout IC (ROIC) and its fabrication technology. Surface micromaching of sensor array are co-designed with TSV fabrication processes to enable TSVs for electrical signals output from backside in sensor chip, sensor chip and its corresponding ROIC chip are vertically stacked, and chip to chip interconnection is achieved by Cu/Sn-Cu microbump bonding. The stacked structure are then assembled to relized MEMS-CMOS 3D heterogeneous integration. Overall, the present work describes an approach for high density MEMS integration. View full abstract»

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  • Electrochemical analysis of cathode in TSV copper electroplating

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    In TSV copper electroplating, the most important is to form the “bottom up” deposition. In order to achieve this kind of super-filling, additive in the electroplating bath need to play its own role at the respective position. Accelerator adsorb at the bottom of the via to accelerate the deposition of copper while suppressor mostly adsorb at the top of the via to inhibit the deposition. Therefore, vias could be supper-filled without any void. In this paper, bis(3-sulfopropyl) disulfide (SPS) and polyethylene glycol (PEG) were used as accelerator and suppressor respectively. The supper-filling mechanism and the competitive adsorption of SPS and PEG were being researched by means of linear sweep voltammetry (LSV) and cyclic voltammogram (CV). The electrochemical analysis and the experimental plating are closely related. View full abstract»

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