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Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

Date 12-14 Nov. 2012

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Displaying Results 1 - 25 of 103
  • [Front cover]

    Publication Year: 2012 , Page(s): 1
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  • Table of contents

    Publication Year: 2012 , Page(s): iv - xiii
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  • Author index

    Publication Year: 2012 , Page(s): 397 - 404
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  • Welcome message

    Publication Year: 2012 , Page(s): 1 - 14
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  • The first 22nm IA multi-CPU and GPU system-on-chip using tri-gate transistors

    Publication Year: 2012 , Page(s): 9 - 12
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB) |  | HTML iconHTML  

    This paper will go over some of the details of Intel's latest Core offering, the first 22nm design code-named Ivy Bridge. In addition to the new process, Ivy Bridge offers several new features including significant improvements to the Graphics and Media block including DX11 support, new power/thermal control optimizations, support for 3 simultaneous displays, new security features and new PCIE Gen3 support. The new 22nm process provides exceptional low voltage performance advantage as well as a 2x improvement in density. The paper also reviews changes to leverage the low operating voltages as well as details of IO, PLL and clocking. Ivy Bridge was introduced into the market on April 23, 2012. View full abstract»

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  • A 1.94mm2, 38.17mW dual VP8/H.264 Full-HD encoder/decoder LSI for Social Network Services (SNS) over smart-phones

    Publication Year: 2012 , Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video data and frame rates for network services. Two fast algorithms and new bool encoder/decoder are proposed to enhance power efficiency. This chip consumes 28.15mW and 10.02mW of VP8 encoder and decoder average power for 1080p@30fps at 0.9V, respectively. View full abstract»

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  • A high performance 64Gb MLC NAND flash memory in 20nm CMOS technology

    Publication Year: 2012 , Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (905 KB) |  | HTML iconHTML  

    A 64Gb MLC NAND flash memory on 20nm CMOS technology has been developed. 135mm2 chip size is realized by 1-sided All-Bit-Line architecture and 128 cells in a string. 25MB/s program throughput with 2-bit/cell is achieved by reducing BL resistance and pump output loading using new BL control method and multi-split block decoder. This device also supports 400MB/s high speed interface. View full abstract»

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  • The 3.0GHz 64-thread SPARC T4 processor

    Publication Year: 2012 , Page(s): 21 - 24
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    The SPARC T4 processor introduces the next generation multi-threaded S3 core and delivers a significant single-thread performance improvement over its predecessor. The chip integrates eight S3 cores, an 8-Bank 4MB L3 Cache, a 768GB/sec crossbar, a memory controller, PCI Gen2.0, 10G Ethernet and a cache coherency controller with 2.4Tb/s highspeed I/Os. The dual-issue, out-of-order execution core features a 16-stage integer pipeline, extensive branch predictions, dynamic threading and an enhanced cryptographic processing unit. The 406mm2 die is fabricated in TSMC's 40nm process and contains 855million transistors and 2.6million flip-flops in a flipchip ceramic package. Enhanced physical design methodologies and extensive power management features enable 3.0GHz operation in the same power envelope of its predecessor. View full abstract»

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  • On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT

    Publication Year: 2012 , Page(s): 25 - 28
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    A compact on-chip SIDO DC-DC converter is proposed for portable equipments operating with a battery or a solar cell. A current up to 30mA is supplied with own transistors in an internal drive mode and more than 100mA by utilizing external power transistors in an external drive mode. The efficiencies are 85% and 84% for each case. A cross regulation problem is solved by inserting an extra cycle before switching the outputs. For solar cell operation, two features are implemented. Any kind of maximum power point tracking MPPT is available by receiving a clock signal calculated by a micro-computer. The converter exploits 99% of the expected maximum power of a solar cell. Backward current protection reduces a leak current by three orders without any performance losses when the light is not available like as in the night. View full abstract»

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  • A sub-400 fJ/bit thermal tuner for optical resonant ring modulators in 40 nm CMOS

    Publication Year: 2012 , Page(s): 29 - 32
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB) |  | HTML iconHTML  

    Optical ring modulators are highly susceptible to external temperature noise and to self-heating from absorbed optical power. We mitigate both problems through circuit techniques. A control loop at the ring measures output power and controls a local heater to compensate for external temperature noise. A control loop at the receiver dynamically tracks DC variations to compensate for self-heating effects. The design has been implemented in a 40 nm TSMC technology. View full abstract»

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  • A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

    Publication Year: 2012 , Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (385 KB) |  | HTML iconHTML  

    This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μW at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/MHz. The core area is 0.037mm2. View full abstract»

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  • A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

    Publication Year: 2012 , Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (533 KB) |  | HTML iconHTML  

    This paper describes the design of a 0.5-6.6Gb/s fully-adaptive low-power quad transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a wide input common-mode circuit and a 3-stage CTLE to remove the immediate post-cursor ISI. The CTLE is fully adaptive using sign-sign LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The transceiver achieves BER <; 10-15 at 6.6Gb/s over an 18dB loss channel. Power consumption is 129mW from 1.2V and 1V supplies. View full abstract»

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  • Expectations for the semiconductor technologies in EVs and HVs

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    EVs and HVs will have a certain share in the future market place. To populate these vehicles, the semiconductor technologies will play a central role. And those technologies will be crucial for the quality of EVs and HVs. To populate EV and HVs, cost will be the most critical factor even in the future. The portion of battery cost will still be large compared to inverter and motor cost. Therefore there is a need of cutting the cost of batteries for EVs and HVs. To do so, there are some technologies undergoing. These technologies are presented and expectations for the semiconductor technologies are explained. View full abstract»

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  • Semiconductor memory scaling and beyond

    Publication Year: 2012 , Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1067 KB) |  | HTML iconHTML  

    Semiconductor is an indispensible component of modern electronic systems. The history of the semiconductor industry is namely the history of scaling that has consequently benefited consumers by advancing the mobile era by providing high density product at low price. Besides, every semiconductor memory company is facing the ultimate physical limit of scaling. Natural question arising here is “What will be the next?”. As parts of efforts to overcome those limits and grasp new opportunities under new environment, where meeting requirements of power consumption and data bandwidth in addition to memory density is much more difficult while the importance of them is increasing, new technologies including 3D-IC and non-volatile new memories are currently being researched and developed. View full abstract»

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  • Integrated circuits and systems toward smart ubiquitous patient-centered medical environment

    Publication Year: 2012 , Page(s): 121 - 124
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB) |  | HTML iconHTML  

    Integrated circuits and systems have emerged to play a critical role in supporting the patient-centered medical home (PCMH) model of health care delivery. PCMH model of care has been performed in National Taiwan University Hospital (NTUH), Taiwan. The wireless ECG monitoring devices capable of measuring nonlinear heart rate variability and providing GPS localization information help the cardiologists to better handle the emergency condition of heart failure. A multi-modal signaling processor has been integrated to address patient with acute coronary syndrome, ischemic stroke and subarachnoid hemorrhage and facilitate early detection of targeted events. Electro-sensing antibody probing system has also been realized for biomedical samples. The service package of Telecare center of NTUH is composed of synchronous transmission of biometrics, mutual telephone communication, and rapid decision-making support. By integrating the bio-medical MEMS sensors with silicon circuits into mobile phones, physiological signals and vital signs can be monitored at any place and any time. With the mobile phone as a personal medical information hub, the biometrics can be sent to cloud for real-time monitoring and further analysis. View full abstract»

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  • Technology challenges and opportunities for ubiquitous computing

    Publication Year: 2012 , Page(s): 125 - 128
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (718 KB) |  | HTML iconHTML  

    Unprecedented transistor integration capacity will be available to make computing truly ubiquitous, but the energy consumption will be a major challenge. Compute energy can be reduced by employing near threshold voltage operation. However, data movement energy will become prohibitive. Software will have to be cognizant of data locality, with introspection for fine grain energy management. The entire stack has to participate in implementing resiliency. Such a holistic system approach will make computing truly ubiquitous. View full abstract»

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  • An energy-efficient BBPLL-based force-balanced Wheatstone bridge sensor-to-digital interface in 130nm CMOS

    Publication Year: 2012 , Page(s): 41 - 44
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB) |  | HTML iconHTML  

    An energy-efficient time-based sensor interface in 130nm CMOS technology is presented for resistive sensors. Traditionally resistive sensors are interfaced with a voltage divider or a Wheatstone bridge to transform the sensor signal to a voltage. However, both the voltage divider and the unbalanced Wheatstone bridge are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture, that offers the advantage of low power consumption with highly improved overall PSRR. It has a noise-frequency-independent PSRR of 52dB for in-band supply noise and supply noise amplitudes up to +10dBFS, which is an improvement of 46dB over the voltage divider and of 26dB over the unbalanced Wheatstone bridge. Apart from the sensor calibration, no other calibration or absolute precise clock or voltage references are needed due to the BBPLL-based architecture. The complete interface consumes only 124.5μW from a 1V supply with 10kHz input bandwidth and 10.4 bit resolution and 8.9 bit linearity, resulting in a state-of-the-art sensor Figure of Merit of 13.03 pJ/conversion. View full abstract»

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  • An integrated 12-V electret earphone driver with symmetric Cockcroft-Walton pumping topology for in-ear hearing aids

    Publication Year: 2012 , Page(s): 45 - 48
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    Electret-type earphone exhibits a great potential on in-ear hearing-aid applications for the low driving power requirement. However, to enable a static force for thin film's vibration, the input voltage swing has to be large. Instead of using HV technology, in this work we develop a 12-V bridge-type audio driving system by a standard 1.8-V 0.18-μm CMOS. The system integrates two switched-capacitor voltage multipliers, asynchronous regulation loops, and switching-type high-voltage drivers. The proposed symmetric Cockcroft-Walton topology can use MOS thin gate as charging capacitors to save 50% on-chip capacitor area. With differential 12-V output, the maximum output driving current is above 400μA. The peak sound pressure for single audio channel is above 80dß with the open-loop THD+N better than 0.6%. View full abstract»

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  • A chopper stabilized instrumentation amplifier with dual DC cancellation servo loops for biomedicai applications

    Publication Year: 2012 , Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (895 KB) |  | HTML iconHTML  

    A 1V 65nm 4.3μW differential difference amplifier based instrumentation amplifier for biomedical applications has been presented. To eliminate the DC baseline drift of the biomedical signals, novel and efficient fine-coarse DC offset cancellation servo loops have been proposed. Measured results show that the proposed instrumentation amplifier achieves 0.8μVrms input referred noise from 0.5Hz to 200Hz with inband gain of 65.5V/V and noise efficiency factor of 5.7 for electrocardiograph signal monitoring. View full abstract»

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  • A 20 μV/°C digital offset compensation technique for comparators and differential amplifiers

    Publication Year: 2012 , Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (635 KB) |  | HTML iconHTML  

    Digital offset compensation has been widely used for start-up calibration of analog ICs. It can be valuable in the design of an offset control circuit that has a minimal dependence on temperature. This eliminates the need to recalibrate the circuit during normal operation when the temperature may randomly fluctuate. This paper presents a gm-tracking technique used in an offset correction loop that drifts only 20 μV/°C over a temperature range of 0°C to 100°C. Test circuits fabricated in a 40 nm CMOS technology confirm the performance of the proposed technique. View full abstract»

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  • Adaptive program verify scheme for improving NAND flash memory performance and lifespan

    Publication Year: 2012 , Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    Since NAND Hash memory program/erase (PE) cycling gradually degrades the reliability of memory cells, the redundancy of error-correction code (ECC) is determined so as to sufficiently ensure the PE cycling endurance at the end of memory lifetime. Therefore, ECC redundancy is under-utilized when PE cycling number is relatively small at the early lifetime. Considering the variations on program speed and error rate depending on the program step pulse voltage (ΔVpp) in the incremental step pulse programming (ISPP), an adaptive ΔVpp scheme was proposed in order to improve program performance by exploiting the under-utilized ECC. However, the adaptive ΔVpp scheme missed the problem of increased voltage stress on memory cells at a large ΔVpp. The voltage stress will shorten the lifespan of Hash memory devices. This paper proposes an adaptive Vverify scheme, which trades the under-utilized ECC for improving program performance at the early lifetime of Hash memory without decreasing the memory lifetime. The experiments with real NAND Hash chips demonstrate up to 21% of program time improvement and 10% of lifetime improvement over the fixed Vverify scheme. View full abstract»

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  • An efficient BCH decoder with 124-bit correctability for multi-channel SSD applications

    Publication Year: 2012 , Page(s): 61 - 64
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency. View full abstract»

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  • A 250-MHz 18-Mb full ternary CAM with low voltage match line sense amplifier in 65nm CMOS

    Publication Year: 2012 , Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    An 18Mb full ternary CAM with low voltage match line sense amplifier (LV-MA) is designed and fabricated in 65-nm bulk CMOS process. The die size is 99.06 mm2. The proposed LV-MA reduces the dynamic power consumption of match-lines to 33% compared to conventional one and realizes 42 % fast match-line sensing. The power consumption of fully paralleled search operation at 125-MHz is 5.1 W, which is 63% smaller than previous work. At 1.0V typical supply voltage, the 250-MHz search frequency is achieved. View full abstract»

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  • An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

    Publication Year: 2012 , Page(s): 69 - 72
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1608 KB) |  | HTML iconHTML  

    Embedded energy monitoring of critical system components can be used to enable better power management by capturing run time system conditions such as temperature and application load. In this work, an energy sensing circuit that provides digitally represented absolute energy per operation of a 128kbit SRAM is presented. Designed in a 65nm low-power CMOS process, SRAMs can operate down to 370 mV. Energy sensing circuit consumes 16.7μW during sensing at 1.2V (only 0.28% of SRAM active power at the same voltage). For improved performance, SRAMs utilize body-biased PMOS input strong-arm type sense amplifiers that can achieve 45% tighter input offset distribution for only ~3.5% of total SRAM area overhead. View full abstract»

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  • A 0.2V 16Kb 9T SRAM with bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency

    Publication Year: 2012 , Page(s): 73 - 76
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (662 KB) |  | HTML iconHTML  

    An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS (MTCMOS) SRAM array implemented with higher-Vth (HVT) devices. The inserted tiny CAM conceals the slow data development after data flipping, and therefore improves overall operating frequency in the near threshold region. A 16Kb SRAM test chip was fabricated in 65nm CMOS technology and showed the minimum energy of 0.33 pJ at 0.4V. View full abstract»

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