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Advanced Packaging Materials (APM), 2013 IEEE International Symposium on

Date Feb. 27 2013-March 1 2013

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Displaying Results 1 - 25 of 36
  • Electromigration failures at Cu/Sn joint interface

    Publication Year: 2013 , Page(s): 32 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB) |  | HTML iconHTML  

    Stressed by a high current density, several EM-induced reliability issues would likely occur at the flip-chip Cu/Sn joint interface. At the cathode interface, EM-induced Cu-pad consumption occurred at the current-entry point (maximum current-density) and voiding occurred at the other joint corner away from the current-entry point (minimum current-density). At the anode interface, EM-enhanced Kirkendall voids coalesced into a gap at the Cu3Sn/Cu interface near the current-exit corner. We believe that the above various EM-induced failure modes were resulted from different current-stressing densities at the joint interfaces. Also, a rare EM failure at the anode interface was found and would be discussed in this study. View full abstract»

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  • A novel type of stacked package and assembling method on the SOC

    Publication Year: 2013 , Page(s): 4 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    This paper proposes a new 3-D stacked package structure and assembling method, which can be widely used on the system-on-chip (SOC). This present package increases the area of the bottom of the substrate and solders square compact structure for signal transmission around the substrate. Meanwhile, it also removes the solder balls on the bottom of the substrate and coats with the radiating layer. So this package can solve the height and heat issues. This proposed assembling method achieves electrical interconnection between the stacked package and the printed-circuit-board (PCB) by inserting the stacked package into the slot that is designed specially and welded on the PCB. This method makes the stacked package reworked much easier than other relevant assembling methods. View full abstract»

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  • Volume shrinkage induced by interfacial reactions in micro joints

    Publication Year: 2013 , Page(s): 8 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (727 KB) |  | HTML iconHTML  

    In 3D-IC, solder joints of a few microns in size are used. Theoretically, there is 11.4% shrinkage in volume when Ni reacted with Sn to form Ni3Sn4. Surface profilometer and SEM analysis were carried out to measure the actual volume shrinkage for micro Ni/Sn/Ni sandwich structures during an isothermal annealing at 180°C for 0-7 days. The results showed there was about 7.3% shrinkage in volume and the remaining 3.2% shrinkage was released by forming voids. The internal stress and the forming of voids caused by solid state reaction might induce potential reliability issues. View full abstract»

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  • Optimized Cu Pillar Bump flip chip package design for ultralow k device application

    Publication Year: 2013 , Page(s): 15 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1925 KB) |  | HTML iconHTML  

    The demand for Cu Pillar Bump (CPB) has been significantly increased due to the fine pitch, high bandwidth, and high thermal performance requirement. However, the Cu pillar also has its own defect for the high peeling stress on the low K layer compare to the eutectic solder bump. To overcome the high peeling stress defect, optimize the CPB design is very important. This paper has three major topics using simulation results to analyze the silicon surface peeling stress. 1. The bump structure optimization, with the Cu pillar adhesion force on different material layers. 2. The solder joint condition impact. 3. The substrate material selection. Each topic has multiple design factors, with the CAE (Computer Aid Engineering) simulation result, the maximum silicon surface peeling stress point can be predicted, the bump and substrate structure can be optimized. View full abstract»

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  • Study of signal integrity for a novel stacked cylindrical PoP package

    Publication Year: 2013 , Page(s): 25 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1536 KB) |  | HTML iconHTML  

    The multilayer Package-on-Package (POP) stacking technique is widely applied in the area of portable electronics, which has better flexibility and expansibility. Meanwhile, the signal speed in 3D integration packages increases continuously, which requires package interconnect structure to have good signal integrity. In this paper, based on a novel stacked cylindrical POP package structure, a design about the noise interference problem of signal transmission between the neighboring layers of chip and the approach to improve signal quality is present by building equivalent models. In the different height and radius cases, a comparison between cylindrical POP package and traditional POP package indicates that the former has superiority on signal integrity. View full abstract»

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  • Silver-indium phase diagram and its applications to electronic packaging

    Publication Year: 2013 , Page(s): 36 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1174 KB) |  | HTML iconHTML  

    In this paper, we will review the silver-indium (Ag-In) phase diagram and explores its unique features that enable the development of new bonding processes for electronic packaging. Its melting range covers 156°C to 952°C, from In melting point to Ag melting point. It consists of three intermetallic compounds (IMC), AgIn2, and Ag2In, and Ag3In, and a solid solution (Ag). Our experimental results do not show the Ag3In compound. In a Ag-rich joint design, only Ag2In and (Ag) show up. By further annealing at 250°C for 350 hours or 400°C for 5 hours, Ag2In converts to (Ag) by reacting with Ag. With the proper structure to begin with, a joint can be made at 180°C that contains only Ag2In and (Ag), achieving a melting temperature of 600°C. Annealing to convert Ag2In to (Ag) will increase the melting to higher than 800°C. Accordingly, various processes can be designed and developed for different packaging applications ranging from automotive electronics, high temperature electronics, and oil exploration. View full abstract»

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  • The fluxless soldering process without intermetallic compounds

    Publication Year: 2013 , Page(s): 44 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3549 KB) |  | HTML iconHTML  

    Basic soldering is a chemical reaction between the solder element such as tin (Sn) and the base metal such as copper (Cu) or nickel (Ni), producing intermetallic compound (IMC) such as Cu6Sn5 or Ni3Sn4. It is the IMC that connects the solder to the metal. The IMC layer grows with time during usage, resulting in potential reliability issues. In this research, we looked into and developed soldering processes that do not produce IMC. The fundamental concept is to choose barrier metal that does not form IMC with the solder. An example is chromium (Cr). Several bonding experiments have been performed. Preliminary results seem to show that high quality Sn solder joints could be made without IMC and without the use of flux. View full abstract»

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  • Electrodeposition of Au-Sn alloys for lead-free solders: Au-rich eutectic and Sn-rich eutectic compositions

    Publication Year: 2013 , Page(s): 52 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3552 KB) |  | HTML iconHTML  

    The Au-Sn binary phase diagram shows that there are two eutectic alloy compositions. The first one is at ~30 at% Sn (Au-rich) with a melting point of 280°C and the second composition is at ~94 at% Sn (Sn-rich) with an eutectic temperature at 217°C. This paper summarizes work that demonstrates that both eutectic alloys can be electrodeposited from electrolytes that are non-toxic and environmentally friendly. The Au-rich eutectic alloy is electrodeposited as alternating layers of Au5Sn and AuSn, while the Sn-rich eutectic alloy is electrodeposited as sequential Au5Sn and Sn layers. In both cases, the entire electrodeposition process is achieved using a single solution, for each eutectic composition, without exposing the sample to air during electrodeposition. Each phase composition is attained by varying the current density only. The microstructure of as-deposited and reflowed solders is characterized and confirmed using X-ray diffraction and scanning electron microscopy. View full abstract»

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  • The effect of iso-thermal aging on vibrational performance of SAC 105 and 305 alloys

    Publication Year: 2013 , Page(s): 69 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2963 KB) |  | HTML iconHTML  

    Ball grid array (BGA) packages have rapidly become the popular choice of manufacturers in the semiconductor industry over the past decade. The characteristics of BGA packages in a vibration environment have a deleterious effect after long term isothermal aging. The effectiveness of this characteristics was demonstrated with promising results through vibration testing of SAC 105 and 305 alloys. This experiment focuses on the vibration fatigue life of 10 mm, 15 mm and 19 mm BGA solder-joints at aging temperatures of 55°C for 6, 12 and 24 months. The deleterious effect of the on the characteristic fatigue lifetime is reported. The results show that the aging time has a direct impact on the total time to failure. The results show that the Time-To-Failure (TTF) of the solder joint decreases with aging. A step stress test approach was taken in selecting a vibration profile for the study in order to reduce the duration of the test with most failures and as to record the failure more precisely over aging across 6,12 and 24 months. The paper concludes with discussion of the deterioration intensity aging has on SAC alloys and the change in reliability over time. The results obtained in this work show that there is a significant deleterious effect on the mechanical strength of SAC alloy solder balls during elevated temperature aging. The data demonstrate that the low-silver-content alloy (SAC105) is more sensitive to elevated temperature aging. View full abstract»

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  • A study of solder alloy ductility for cryogenic applications

    Publication Year: 2013 , Page(s): 82 - 88
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    For aerospace applications it is important to understand the mechanical performance of components at the extreme temperature conditions seen in service. For solder alloys used in microelectronics, cryogenic temperatures can prove problematic. At low temperatures Sn-based solders undergo a ductile to brittle transition that leads to brittle cracks, which can result in catastrophic failure of electronic components, assemblies and spacecraft payloads. As industrial processes begin to move away from Pb-Sn solder, it is even more critical to characterize the behavior of alternative Sn-based solders. Here we report on initial investigations using a modified Charpy test apparatus to characterize the ductile to brittle transformation temperature of nine different solder systems. View full abstract»

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  • A novel stacking method of filling hole used in package on package

    Publication Year: 2013 , Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (603 KB) |  | HTML iconHTML  

    With the developing of the electronics industry, 3-D package stack has been a new trend. Currently, most of the package on package (POP) stack adopted the bump interconnection with the solder balls, resulted in some issues, such as bridging, shifting and warpage. In this paper, a novel stacking method is presented to solve the problems of interconnection and stacking accuracy mentioned above. The insulating medium was adhered to the substrate; a hole was drilled according to the interconnection requirement. Then the hole is filled with copper and interconnects the substrates through the insulating medium. Meanwhile, this lead-free soldering stacking method of filling hole adapt to the global green manufacturing trend. View full abstract»

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  • Packaging materials for 2.5/3D technology

    Publication Year: 2013 , Page(s): 93 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2740 KB) |  | HTML iconHTML  

    The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level/pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF). View full abstract»

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  • Au and Pd embrittlement in space-confined soldering reactions for 3D IC applications

    Publication Year: 2013 , Page(s): 102 - 112
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1567 KB) |  | HTML iconHTML  

    Soldering reactions under space confinement has become increasingly important due to its application for chip stacking in three-dimensional integrated circuits (3D ICs. This study reports the effects of Au, from the dissolution of surface finishes, in such space-confined solder joints. Our results indicate that (Au,Ni)Sn4 can form a continuous layer across the entire of the joint, even when Au is very thin. This morphology is detrimental to the joint reliability. In other words, the so-called gold embrittlement has becomes relevant in 3D IC packaging. Pd is one of the most commonly used materials for surface finishes. The effects of Pd will also be discussed. In addition, solutions to solve the Au and Pd embrittlement are presented in this work. View full abstract»

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  • Effects of Ag concentration on the Ni-Sn interfacial reaction for 3D-IC applications

    Publication Year: 2013 , Page(s): 113 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1063 KB) |  | HTML iconHTML  

    Ni/Sn solid-state reaction might induce the void formation with low-volume solder under a severe space confinement in 3D IC packaging, and Ag addition could effectively eliminate void formation. In the present study, the different Ag concentration in solder was carried out to figure out the lower limit of Ag concentration to avoid void formation. The solid-state diffusion couple, Ni/Sn-xAg/Ni (x = 0 wt.%, 1.0 wt.%, 2.4 wt.%, 3.5 wt.%, 4.5 wt.%, 8.0 wt.%), was prepared by thermal compression. The isothermal aging process was carried out at 200°C. There were only two IMCs being observed during the entire aging process: Ag3Sn and Ni3Sn4. The Ag3Sn initially formed as fine and eutectic network in the Sn matrix after cooling. The Ag3Sn particles were found eventually located at the middle of sandwich structure. After Sn was totally consumed, there was very different microstructure in the sandwich structure in different Ag concentration. View full abstract»

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  • MEMS in laminates and package substrates

    Publication Year: 2013 , Page(s): 121 - 125
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB) |  | HTML iconHTML  

    Post semiconductor manufacturing processes (PSM), including packaging and printed circuit board (PCB) technologies with a few micrometer line and space resolution and sub-mil vias are readily achievable. Such PSM technology can be used to manufacture micro electromechanical systems (MEMS) for sensing and actuation applications, which are traditionally produced using silicon processes. A lamination-based manufacturing process allows for a broader selection of materials and fabrication processes than silicon-based manufacturing, and therefore provides greater design freedom for producing functional microdevices. In many cases devices can be fabricated that are more suited to their applications than their silicon counterparts. Furthermore, such microdevices can be built with a high degree of integration, pre-packaged, and at low cost. Indeed, the PCB and packaging industries stand to benefit greatly by expanding their offerings beyond serving the semiconductor industry and developing their own devices and products. This paper illustrates that good quality MEMS devices can be manufactured in laminates, and discusses some of the unique benefits of such devices. This laminate MEMS technology promises for not only manufacturing microdevices but also heterogeneously integrating them with silicon microelectronics into their package with the same manufacturing processes. View full abstract»

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  • Thermal-mechanical simulation of embedded module based on organic substrate

    Publication Year: 2013 , Page(s): 126 - 136
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1659 KB) |  | HTML iconHTML  

    Embedded devices encapsulated by electronic packaging offer significant advantages in terms of miniaturization, cost and performance. A new packaging concept, Embedded Technology, is highly conducive to the aforementioned advantages where active components are directly embedded into organic substrates without incurring subsequent package assembly processes such as flip-chip technology. However, one of the most significant drawbacks of Embedded Technology is its inherently poor thermal characteristics, which is symptomatic of most embedded device topologies. This paper presents a practical, streamline thermal management design methodology that mitigates thermal-mechanical risks of Embedded Technology while balancing electrical performance and cost considerations. The proposed methodology first demonstrates that the associated thermal-mechanical weaknesses of Embedded Technology can be mitigated through judicious selection of an appropriate substrate with good thermal conductivity, low Coefficient of Thermal Expansion (CTE) and high degree of hermeticity. A heuristic thermal-mechanical study of an embedded power MOSFET module is exemplified in this paper; its thermal performance is characterized under both steady-state and transient conditions thereby highlighting the embedded module's sensitivity to material properties and convection properties. A power MOSFET bare die from Alpha & Omega Semiconductor Co. is applied in this embedded module. Thermal management characterization of the structure is subsequently scrutinized under different loading conditions, which can be done efficiently by numerical studies based on Finite Element Analyses (FEA). Simulation results reveal that the thermal-mechanical properties of the embedded module under forced-convection are much better compared to the properties under natural-convection. The thermal performance of the embedded module under forced convection conditions is sensitive to changes in temperature. Lastly, thermal-me- hanical simulations depict elevated stress concentrations appearing at the central portion of the MOSFET die edge, which could lead to potential brittle fracture. Qualitative correlation of the predicted stress contours with observed cross-sectioned SEM samples demonstrate that mitigating measures can be incorporated into the baseline simulation environment, a priori, to truncate product design iterations and improve process reliability. View full abstract»

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  • Newly developed ultralow CTE materials for thinner PKG applications

    Publication Year: 2013 , Page(s): 137 - 145
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2050 KB) |  | HTML iconHTML  

    The higher density packaging technologies have been required to reduce the area of substrate for smaller portable handheld products and devices such as smart phones and tablet PCs. So, the three-dimensional packaging is becoming to be a key technology to minimize the total size of products and devices. However, the thinner construction of PoP (package on package) may cause the poor connection reliability because of the warpage of the substrate at the soldering process. So, the reduction of the warpage of the substrate by the ultralow CTE (coefficient of thermal expansion) materials may be the key to overcome. Recently, we have developed two types of ultralow CTE materials to meet with the requirement applying our new resin systems and a filler treatment technology. The developed materials show the ultralow CTE(X) of 2.8-3.3 ppm/OC which is close to that of the glass fabric. The resulted warpage using the material is much lower than that of the conventional low CTE material. We are also developing a technology for the further lowering of CTE for future applications. View full abstract»

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  • Performance Analysis of Low Stress Ultra-Low Dielectric Coatings for High Density Substrates

    Publication Year: 2013 , Page(s): 146 - 153
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1055 KB) |  | HTML iconHTML  

    A major shortcoming that prevented present-day organic substrates and interposers from achieving high VOs at fine pitch and dimensional stability are thermal expansion mismatches between material layers and requirement of low dielectric constant to improve signal transmission. Low-stress materials with ultra-low dielectric coefficient can be used to improve signal transmission and to relieve stresses in circuits on silicon, glass and polymeric substrates. The electrical performance of metallic circuits on newly developed porous materials is investigated in this study. Experimental results showed that the impedance performance of circuit is significantly improved with the new material. Mechanical testing showed that the elastic modulus of the new material is only 1/5 of the conventional polymer, and stresses can be relieved using the by the low elastic modulus, ultralow dielectric material. View full abstract»

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  • Microsolder ball incorporated nanofiber anisotropic conductive adhesives (microsolder/nanofiber ACAs)

    Publication Year: 2013 , Page(s): 162 - 169
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1437 KB) |  | HTML iconHTML  

    We suggest and investigate a new concept of nanofiber ACA that incorporates microsolder balls into nanofiber to obtain stable three-dimensional electrical properties of fine pitch electronics. This adhesive offers many advantages, such as suppressing microsolder ball movement during resin flow, perfect X-Y axes insulation at 25 μm fine pitch, and easy fine solder ball handling. Microsolder balls can be successfully incorporated into a nanofiber structure through an electrospinning process, and they have good solderability within the nanofiber/epoxy matrix. View full abstract»

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  • Next generation transition liquid phase sintering pastes for Z-Axis interconnection in sub-400 micron pitch high density interconnect

    Publication Year: 2013 , Page(s): 170 - 177
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1838 KB)  

    Paste-filled-via interconnects were introduced to the electronics packaging industry in the mid 1990's. Since then, implementation of paste interconnection has grown to encompass a number of different package architectures. Transient liguid phase sintering (TLPS) pastes are a unigue family of paste materials that form a continuous metallurgically alloyed pathway from the upper pad, through the bulk of the paste in the via, to the lower pad during a standard lamination cycle. The TLPS alloying reaction produces an interconnect that is highly electrically and thermally conductive and robust enough to withstand multiple lead-free solder reflow cycles. In North America, the primary implementation has been in complex PCBs where the circuit board is built as a number of sub-cores that are then interconnected in a single lamination with TLPS pastes in vias laser ablated into prepreg or adhesive layers applied to the sub-cores. The second type of architecture that most benefits from a TLPS z-axis interconnection strategy is HDI for mobile electronic products. The high reliability, stackability and anywhere, any layer placement of TLPS-paste vias enables very high density, thin, lightweight designs. To fully exploit this market segment; however, the TLPS interconnect strategy must provide a pathway to achieve sub 400 micron pitch designs and via sizes below 125 micron. While the existing TLPS paste technology is capable of addressing some of this segment, next generation materials will be needed. Newly developed TLPS pastes with very high metal loading - a 30% volumetric improvement over the previous generation - offer lower and more consistent electrical resistivity, higher strength to withstand expansion in the z-axis, a dense fill in via sizes as small as 50 micron, and improved resistance stability in thermal cycling of daisy chain constructions. View full abstract»

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  • Thermal management in high layer count PCBs using sintered-paste-filled PTH

    Publication Year: 2013 , Page(s): 178 - 185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1712 KB)  

    Thermal management is becoming increasingly important throughout the electronic packaging industry. In the high-layer-count printed circuit board (PCB) market for applications such as servers and modems, plated through holes (PTH) are used for both electrical interconnection and as thermal drains. In order to take maximum advantage of the PTH as a thermal conductor, it is becoming increasingly common to fully plate up the PTH to closure. Although this provides excellent thermal conduction, this process is very lengthy, costly and prone to a number of pitfalls. In many cases, the requirement for the product is to exceed the thermal conduction of the more common epoxy-filled PTH, but the level of thermal conduction provided by the plated-closed PTH is far in excess of this requirement. Highly-metal-loaded (97% net by weight) transient liquid phase sintering (TLPS) pastes offer an attractive intermediate solution. In an experiment on a typical high-layer-count PCB configuration with 0.62 mm diameter holes on a 1.34 mm pitch with 0.013 copper thickness in the barrel and a 2.34mm board thickness, the fully- plated-shut copper architecture was modeled and calculated to be 67 W/mK effective thermal conductivity, the conventional epoxy-fill in PTH approach calculated as 4 W/mK, and the TLPS-paste-filled PTH was calculated to be 11 W/mK. The TLPS paste was then installed in the PCB using conventional pressure head hole-filling equipment, and the effective thermal conductivity was measured to be 10.9 W/mK - in excellent agreement with the model. It is also worth noting that the modeled performance of the TLPS paste in a non-plated through hole exceeded the modeled value for the conventional epoxy-in-PTH solution by 47%. The use of TLPS-paste-filled PTH thus offers a high performance solution at a fraction of the cost of plating to closure. View full abstract»

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  • Fine pitch chip on board (CoB) bonding using B-stage non-conductive film (NCF) for 3D TSV vertical interconnection

    Publication Year: 2013 , Page(s): 186 - 191
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    In this study, the CoB bonding using NCF was investigated for the 3D-TSV interconnection as a noble way for compensating the former processes such as fluxing and underfill process. The whole processes using NCF were closely investigated. The properties of NCF such as curing behavior, viscosity, modulus, glass transition temperature, and CTE were optimized for CoB bonding. NCFs which have high glass transition temperature and lower thermal expansion coefficient were effective on the enhancing the reliability of CoB structure for 3D-TSV application. As a summary, 3D-TSV vertical interconnection using B-stage wafer-level NCFs was investigated. The CoB bonding using NCFs for 3D-TSV interconnection was successfully investigated with the stable joint interconnection as well as the enhanced reliability. View full abstract»

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  • Low-temperature sintering of a nanosilver paste for attaching large-area power chips

    Publication Year: 2013 , Page(s): 192 - 202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1494 KB) |  | HTML iconHTML  

    A low-temperature silver sintering technology is emerging as a lead-free die-attach solution for high-reliability packaging of power electronics devices and modules. Sintered chips on substrate are reported to have excellent heat dissipation and capability of working at higher junction temperatures. However, one concerning issue with many of the silver sintering die-attach processes is the requirement of large uniaxial stress or pressure, ranging from 10 MPa to 40 MPa, to lower the sintering temperature to about 250°C. In this paper, we report our findings in the evaluation of a nanosilver paste technology developed to eliminate pressure needed for the silver-sintering die-attach process. The nanosilver paste was analyzed by TGA and DSC to show its weight loss and enthalpy characteristics associated with solvent evaporation, binder burn-out, and densification. A custom optical system was used to measure bond-line shrinkage behavior. A fractional factorial design of experiments was carried out to identify the importance and interaction of various processing parameters, such as pressure, temperature and time, on the bond strength and microstructure of sintered nanosilver joints. Based on the findings, a simple die-attach process, consisting of pressure-drying at 180°C under a few MPa pressure, followed by sintering below 260°C with zero pressure was found to produce strong die bonding with strength in excess of 30 MPa. View full abstract»

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  • Improving bend performance of lead-free plastic ball grid array assemblies with thermal curing epoxy and UV curing acrylic edge-bond adhesives

    Publication Year: 2013 , Page(s): 203
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (46 KB)  

    The introduction of lead-free (LF) solder metallurgy have contributed to a gradual reduction in the bend performance of board level interconnects (BLI) of ball grid array (BGA) packages. In this paper, bend performance of lead-free plastic BGA assemblies with thermal curing epoxy and UV curing acrylic edge-bond adhesives was investigated using 3-point bending test. The assemblies without adhesives were also tested for comparison. Four triaxial strain gages were mounted on the board to monitor the PCB strain and verify symmetrical loading. The failure criterion for this study was set as when the daisy chain resistance readings are more than 20% of the normal values. The results show that both the epoxy and acrylic adhesives improve the bend performance of BGA assemblies. The epoxy with higher modulus and adhesion strength compared to acrylic can provide better bend performance. After analyzing three components of each test leg that were dye penetrated using dye-and-pry, cross section, SEM, and EDX. Five failure modes have been identified: (1) PCB pad lift/cratering, (2) fracture at package pad/IMC interface, (3) fracture at PCB pad/IMC interface, (4) fracture within bulk solder, and (5) trace fracture. View full abstract»

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  • Reliability of high I/O FCBGA corner stake materials

    Publication Year: 2013 , Page(s): 204 - 222
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2318 KB) |  | HTML iconHTML  

    Commercial-off-the-shelf area array package (COTS AAP) technologies in high-reliability versions are now being considered for use in a number of electronic systems. Although to improve mechanical resistance of fragile flip-chip die within package, these advanced electronic packages commonly use underfill for the die attachment; full or partial corner underfilling may also be required at the printed circuit board (PCB) level to improve assembly reliability, particularly under mechanical and fatigue loading. This paper first presents a comprehensive summary of literature surveyed on the application of underfill materials, thermal cycle reliability of underfill for flip-chip die with conventional balls, and compare to the recent advanced versions with fine copper-pillar interconnects. Then, it presents reliability due to underfilling at the board level, discussing key parameters that influence thermal cycle and mechanical reliability of AAPs with underfill, edge-bond, and corner stake. Finally, it presents thermal cycle test data with optical and microsectional photomicrographs of a high I/O flip-chip ball grid array (FCBGA) assembled onto PCB and then added corner staking or additional center staking to improve mechanical resistance to vibration and drop testing. Drop test results and failure mechanisms for a 1704 I/O FCBGA package assembly with and without corner/center staking also presented. View full abstract»

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