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VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Date 7-9 April 1992

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  • Digest of Papers. 1992 IEEE VLSI Test Symposium. 10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip (Cat. No.92TH0437-4)

    Publication Year: 1992
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    Freely Available from IEEE
  • Accelerated path delay fault simulation

    Publication Year: 1992 , Page(s): 1 - 6
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (622 KB)  

    Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered.<> View full abstract»

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  • Generalization of independent faults for transition faults

    Publication Year: 1992 , Page(s): 7 - 12
    Cited by:  Papers (6)
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    Independent faults were shown to he effective in computing small test sets for stuck-at faults. An efficient procedure for computing a maximal set of independent stuck-at faults is proposed. The notion of independent faults is then extended to other fault models, specifically, transition faults, that require two-pattern tests. Experimental results are presented to show that the computation of independent faults can be practically performed.<> View full abstract»

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  • Test pattern generation system for delay faults using a high speed simulation processor 'SP'

    Publication Year: 1992 , Page(s): 13 - 18
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    The degree of needs for high quality test pattern sets for delay faults becomes more serious as VLSI chips have more complex structures and higher performance. In spite of its importance, it is more difficult to find complete test pattern sets for delay faults than for stuck-at faults. It thus takes much time to generate high quality test pattern sets. To acquire high quality test pattern sets for delay faults as fast as possible, the authors take an approach that executes a test pattern generation process for delay faults on the very high speed logic simulation processor 'SP'. As a result, to apply ISCAS'89 benchmark circuits, the authors achieved a fault coverage rate of 85% in two minutes testing for a circuit which has about 1000 gates. They confirmed that this system is effective as a pre-processing method to exclude many faults at very highspeed.<> View full abstract»

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  • On test generation for path delay faults in ASICs

    Publication Year: 1992 , Page(s): 19 - 24
    Cited by:  Papers (10)
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    Discusses automatic test pattern generation (ATPG) for path delay faults in application specific integrated circuits (ASICs). An ATPG that uses a modified FAN algorithm to generate tests for critical paths derived using static timing analysis is described. The test generation procedure is optimised through the use of path constrainment and the concept of mandatory assignments.<> View full abstract»

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  • Delay fault testing of iterative arithmetic arrays

    Publication Year: 1992 , Page(s): 25 - 30
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    Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.<> View full abstract»

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  • Scan testing of latch arrays

    Publication Year: 1992 , Page(s): 31 - 36
    Cited by:  Patents (1)
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    A novel scan-based test method that allows latch-based arrays to be fully tested using conventional scan software tools is described. Very little support circuitry and simple modeling are required. Several useful applications of the method are described. The method was used on several production chips.<> View full abstract»

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  • A methodology for the insertion of a hierarchical and boundary-scan compatible self test

    Publication Year: 1992 , Page(s): 37 - 42
    Cited by:  Papers (3)
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    A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy the automatic method for the insertion of self test registers as well as the synthesis of a test control unit is presented. These self testable modules are then combined for arbitrary hierarchy levels using test management units. The concept is embedded within the boundary-scan architecture and the implementation has been integrated into a commercial design framework.<> View full abstract»

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  • The split boundary scan register technique for testing board interconnects

    Publication Year: 1992 , Page(s): 43 - 48
    Cited by:  Papers (5)
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    Presents a new approach to testing board interconnects, on a board containing three-state nets and with chips equipped with the boundary scan architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, the authors have concentrated on the walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of walking 1/0 in linear time.<> View full abstract»

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  • Testability properties of acyclic structures and applications to partial scan design

    Publication Year: 1992 , Page(s): 49 - 54
    Cited by:  Papers (8)  |  Patents (3)
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    It is well known that acyclic sequential structures are considerably easier to test than cyclic sequential circuits. Hence some partial scan techniques attempt to simplify the test generation problem by ensuring that the portion of the circuit effectively under test is acyclic. In such designs the test time is dominated by the shifting of test patterns into and out of the scan path. The authors present a compacting technique that minimizes the number of distinct test patterns required to detect an arbitrary fault, thus minimizing the amount of data shifted in to detect the fault. The technique results in (1) a minimal compacted test schedule and (2) a condensed combinational test generation model, which can be used to generate and apply tests to the circuit in an efficient manner.<> View full abstract»

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  • A design for testability scheme to reduce test application time in full scan

    Publication Year: 1992 , Page(s): 55 - 60
    Cited by:  Papers (37)
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    Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults.<> View full abstract»

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  • Design of low cost ROM based test generators

    Publication Year: 1992 , Page(s): 61 - 66
    Cited by:  Papers (8)
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    A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.<> View full abstract»

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  • On the effectiveness of simultaneous self-test techniques

    Publication Year: 1992 , Page(s): 67 - 72
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    Describes a built-in self-test (BIST) technique for general sequential circuits in which storage elements in a circuit are replaced with self-test elements. These elements are connected as a feedback shift register, and used to both generate test patterns and compress test responses. Benchmarks were run on a number of standard sequential benchmark circuits to determine single stuck-at fault coverage. The results of these tests indicate that the self-test techniques presented obtain fault coverage similar to that of random test techniques.<> View full abstract»

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  • Built-in self-test design for large embedded PLAs

    Publication Year: 1992 , Page(s): 73 - 78
    Cited by:  Papers (1)  |  Patents (1)
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    Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time.<> View full abstract»

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  • Coset error detection in BIST design

    Publication Year: 1992 , Page(s): 79 - 83
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    A finite-field algebraic description of a built-in self-test (BIST) design based on primitive feedback shift registers (LFSRs) implementing the test generator and the signature analyzer (SA) is presented. That the BIST schemes that use the TG and the SA with the same feedback polynomial detect errors which distort the output functions of the circuits-under-test for a set of the input vectors forming a coset of a subspace. The authors term this type of error the 'single coset error'. Signature schemes which detect the coset errors of multiplicity r are further described, (r> View full abstract»

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  • A mixed signal tester solution for: standards traceable AC calibration of analog modules

    Publication Year: 1992 , Page(s): 84 - 89
    Cited by:  Papers (2)
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    Presents a mixed signal test system architecture focused at reducing the overall cost of test. Illustrated are the tester architecture, accuracy and traceability achievements, as well as the benefits realized in the reduction of factors contributing to the overall cost of test.<> View full abstract»

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  • A functional BIST approach for FIR digital filters

    Publication Year: 1992 , Page(s): 90 - 95
    Cited by:  Papers (7)
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    Presents a functional level built-in self-test of digital filters. This BIST technique is based on predetermined patterns which are not dependent on the filter implementation. Many examples show that stuck-at fault coverage is about 98%.<> View full abstract»

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  • Hierarchical fault modeling for analog and mixed-signal circuits

    Publication Year: 1992 , Page(s): 96 - 101
    Cited by:  Papers (36)
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    Presents a comprehensive approach, based on functional error characterization, for modeling faults in analog and mixed-signal circuits. A case study based on a CMOS and an nMOS operational amplifier is discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level.<> View full abstract»

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  • On-line testing of switched-capacitor filters

    Publication Year: 1992 , Page(s): 102 - 106
    Cited by:  Papers (15)
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    Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent test of analog circuits.<> View full abstract»

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  • Robust switch-level test generation

    Publication Year: 1992 , Page(s): 107 - 112
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    Metal oxide semiconductor (MOS) technology is highly popular currently due to the many advantages that it provides. It has been shown that conventional methods of testing are not applicable to MOS circuits. A switch-level model is used to generate a sequence of test vectors for a variety of MOS circuits, including those containing pass transistor logic.<> View full abstract»

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  • On test generation for combinational circuits consisting of AND and EXOR gates

    Publication Year: 1992 , Page(s): 113 - 118
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    Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.<> View full abstract»

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  • An investigation of circuit partitioning for parallel test generation

    Publication Year: 1992 , Page(s): 119 - 124
    Cited by:  Papers (2)  |  Patents (2)
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    Explores the feasibility of using circuit partitioning approach to reduce the run-time complexity of test generation via parallel processing. Characterization of the major phases of test generation is used to show how the inherent parallelism existing in test generation can be exploited during forward implication and backward justification. Upper bounds on the concurrency available in specific are empirically determined by simulating the behavior of a 'perfect' conflict-free test generation algorithm that operates without backtracking. Results presented for a number of benchmark circuits indicate that the average available parallelism is fairly low, limiting the potential speedup of a circuit partitioning approach to test generation.<> View full abstract»

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  • On fault deletion problem in concurrent fault simulation for synchronous sequential circuits

    Publication Year: 1992 , Page(s): 125 - 130
    Cited by:  Papers (4)
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    A method for improving the performance of concurrent fault simulators for combinational and synchronous sequential circuits is proposed. The paper identifies two causes of inefficiencies and a simple and uniform method to eliminate them. A simulator, FASTS, based on the method proposed in the paper is implemented and it is shown that FASTS outperforms the existing concurrent simulation methods proposed in literature.<> View full abstract»

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  • Design of reduced testing for VLSI circuits based on linear code theory

    Publication Year: 1992 , Page(s): 131 - 136
    Cited by:  Papers (1)
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    Pseudo-exhaustive testing can detect all stuck-at faults in combinational circuits. Although the testing time is reduced compared to exhaustive testing, it still remains long. In this paper, a design procedure which requires a minimum number of test vectors to detect all stuck-at faults is presented. The process is based on linear code theory, and different generator polynomials are used to design the LFSR. Fault simulation is used to evaluate the faults detected by each test vector generated consecutively by the LFSR. The LFSR resulting in a minimum number of test vectors is chosen for circuit implementation. The results show that this approach greatly reduces the test time of the actual circuit.<> View full abstract»

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  • BIST linear generator based on complemented outputs

    Publication Year: 1992 , Page(s): 137 - 142
    Cited by:  Papers (7)  |  Patents (28)
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    Autonomous linear finite state machines with both complemented and uncomplemented register outputs (mixed-output ALFSMs) have been investigated for their use as deterministic and pseudo-random test vector generators in a BIST scheme. The authors describe a method for deriving the feedback connections of the mixed-output ALFSM given a deterministic sequence of n n-bit wide test vectors. They also show that the state graph structure is preserved thus enabling the generation of maximum-length sequences if the characteristic polynomial of the connectivity matrix is primitive. An example is given to illustrate the synthesis method of a mixed-output ALFSM based test vector generator. A better solution is obtained compared to conventional uncomplemented output ALFSM.<> View full abstract»

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