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VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Date 7-9 April 1992

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Displaying Results 1 - 25 of 60
  • Digest of Papers. 1992 IEEE VLSI Test Symposium. 10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip (Cat. No.92TH0437-4)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (34 KB)
    Freely Available from IEEE
  • Accelerated path delay fault simulation

    Publication Year: 1992, Page(s):1 - 6
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB)

    Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure... View full abstract»

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  • Generalization of independent faults for transition faults

    Publication Year: 1992, Page(s):7 - 12
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (451 KB)

    Independent faults were shown to he effective in computing small test sets for stuck-at faults. An efficient procedure for computing a maximal set of independent stuck-at faults is proposed. The notion of independent faults is then extended to other fault models, specifically, transition faults, that require two-pattern tests. Experimental results are presented to show that the computation of inde... View full abstract»

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  • Test pattern generation system for delay faults using a high speed simulation processor 'SP'

    Publication Year: 1992, Page(s):13 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The degree of needs for high quality test pattern sets for delay faults becomes more serious as VLSI chips have more complex structures and higher performance. In spite of its importance, it is more difficult to find complete test pattern sets for delay faults than for stuck-at faults. It thus takes much time to generate high quality test pattern sets. To acquire high quality test pattern sets for... View full abstract»

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  • On test generation for path delay faults in ASICs

    Publication Year: 1992, Page(s):19 - 24
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Discusses automatic test pattern generation (ATPG) for path delay faults in application specific integrated circuits (ASICs). An ATPG that uses a modified FAN algorithm to generate tests for critical paths derived using static timing analysis is described. The test generation procedure is optimised through the use of path constrainment and the concept of mandatory assignments.<> View full abstract»

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  • Delay fault testing of iterative arithmetic arrays

    Publication Year: 1992, Page(s):25 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the d... View full abstract»

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  • Scan testing of latch arrays

    Publication Year: 1992, Page(s):31 - 36
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB)

    A novel scan-based test method that allows latch-based arrays to be fully tested using conventional scan software tools is described. Very little support circuitry and simple modeling are required. Several useful applications of the method are described. The method was used on several production chips.<> View full abstract»

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  • A methodology for the insertion of a hierarchical and boundary-scan compatible self test

    Publication Year: 1992, Page(s):37 - 42
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB)

    A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy the automatic method for the insertion of self test registers as well as the synthesis of a test control unit is presented. These self testable modules are then combined for arbitrary hierarchy levels using test management units. The concept... View full abstract»

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  • The split boundary scan register technique for testing board interconnects

    Publication Year: 1992, Page(s):43 - 48
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (445 KB)

    Presents a new approach to testing board interconnects, on a board containing three-state nets and with chips equipped with the boundary scan architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std1149.1-1990 standard. Although most of the algorithms developed so far ca... View full abstract»

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  • Testability properties of acyclic structures and applications to partial scan design

    Publication Year: 1992, Page(s):49 - 54
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    It is well known that acyclic sequential structures are considerably easier to test than cyclic sequential circuits. Hence some partial scan techniques attempt to simplify the test generation problem by ensuring that the portion of the circuit effectively under test is acyclic. In such designs the test time is dominated by the shifting of test patterns into and out of the scan path. The authors pr... View full abstract»

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  • A design for testability scheme to reduce test application time in full scan

    Publication Year: 1992, Page(s):55 - 60
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (506 KB)

    Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of ... View full abstract»

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  • Design of low cost ROM based test generators

    Publication Year: 1992, Page(s):61 - 66
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.<> View full abstract»

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  • On the effectiveness of simultaneous self-test techniques

    Publication Year: 1992, Page(s):67 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (423 KB)

    Describes a built-in self-test (BIST) technique for general sequential circuits in which storage elements in a circuit are replaced with self-test elements. These elements are connected as a feedback shift register, and used to both generate test patterns and compress test responses. Benchmarks were run on a number of standard sequential benchmark circuits to determine single stuck-at fault covera... View full abstract»

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  • Built-in self-test design for large embedded PLAs

    Publication Year: 1992, Page(s):73 - 78
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB)

    Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage c... View full abstract»

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  • Coset error detection in BIST design

    Publication Year: 1992, Page(s):79 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB)

    A finite-field algebraic description of a built-in self-test (BIST) design based on primitive feedback shift registers (LFSRs) implementing the test generator and the signature analyzer (SA) is presented. That the BIST schemes that use the TG and the SA with the same feedback polynomial detect errors which distort the output functions of the circuits-under-test for a set of the input vectors formi... View full abstract»

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  • A mixed signal tester solution for: standards traceable AC calibration of analog modules

    Publication Year: 1992, Page(s):84 - 89
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB)

    Presents a mixed signal test system architecture focused at reducing the overall cost of test. Illustrated are the tester architecture, accuracy and traceability achievements, as well as the benefits realized in the reduction of factors contributing to the overall cost of test.<> View full abstract»

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  • A functional BIST approach for FIR digital filters

    Publication Year: 1992, Page(s):90 - 95
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB)

    Presents a functional level built-in self-test of digital filters. This BIST technique is based on predetermined patterns which are not dependent on the filter implementation. Many examples show that stuck-at fault coverage is about 98%.<> View full abstract»

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  • Hierarchical fault modeling for analog and mixed-signal circuits

    Publication Year: 1992, Page(s):96 - 101
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB)

    Presents a comprehensive approach, based on functional error characterization, for modeling faults in analog and mixed-signal circuits. A case study based on a CMOS and an nMOS operational amplifier is discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level.<> View full abstract»

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  • On-line testing of switched-capacitor filters

    Publication Year: 1992, Page(s):102 - 106
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB)

    Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent ... View full abstract»

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  • Robust switch-level test generation

    Publication Year: 1992, Page(s):107 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Metal oxide semiconductor (MOS) technology is highly popular currently due to the many advantages that it provides. It has been shown that conventional methods of testing are not applicable to MOS circuits. A switch-level model is used to generate a sequence of test vectors for a variety of MOS circuits, including those containing pass transistor logic.<> View full abstract»

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  • On test generation for combinational circuits consisting of AND and EXOR gates

    Publication Year: 1992, Page(s):113 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation p... View full abstract»

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  • An investigation of circuit partitioning for parallel test generation

    Publication Year: 1992, Page(s):119 - 124
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB)

    Explores the feasibility of using circuit partitioning approach to reduce the run-time complexity of test generation via parallel processing. Characterization of the major phases of test generation is used to show how the inherent parallelism existing in test generation can be exploited during forward implication and backward justification. Upper bounds on the concurrency available in specific are... View full abstract»

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  • On fault deletion problem in concurrent fault simulation for synchronous sequential circuits

    Publication Year: 1992, Page(s):125 - 130
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB)

    A method for improving the performance of concurrent fault simulators for combinational and synchronous sequential circuits is proposed. The paper identifies two causes of inefficiencies and a simple and uniform method to eliminate them. A simulator, FASTS, based on the method proposed in the paper is implemented and it is shown that FASTS outperforms the existing concurrent simulation methods pro... View full abstract»

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  • Design of reduced testing for VLSI circuits based on linear code theory

    Publication Year: 1992, Page(s):131 - 136
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB)

    Pseudo-exhaustive testing can detect all stuck-at faults in combinational circuits. Although the testing time is reduced compared to exhaustive testing, it still remains long. In this paper, a design procedure which requires a minimum number of test vectors to detect all stuck-at faults is presented. The process is based on linear code theory, and different generator polynomials are used to design... View full abstract»

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  • BIST linear generator based on complemented outputs

    Publication Year: 1992, Page(s):137 - 142
    Cited by:  Papers (6)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Autonomous linear finite state machines with both complemented and uncomplemented register outputs (mixed-output ALFSMs) have been investigated for their use as deterministic and pseudo-random test vector generators in a BIST scheme. The authors describe a method for deriving the feedback connections of the mixed-output ALFSM given a deterministic sequence of n n-bit wide test vectors. They also s... View full abstract»

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