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VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

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VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date 17-19 June 1999

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Title History

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

Semiconductor industry evolution for 21/sup st/ century

CMOS technology: Present and future

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

A 1 V, 10.4 mW low power DSP core for mobile wireless use

A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure

A 250 MHz CMOS floating-point divider with operand pre-scaling

A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links

840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-processer communication

A low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

Charge sharing concept for power efficiency and EME improvement of boosted charge pumps in NVMs

A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories

A source-line programming scheme for low voltage operation NAND flash memories

A 144 Mb 8-level NAND flash memory with optimized pulse width programming

A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL

GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link

Wide tuning range inversion-mode gated varactor and its application on a 2-GHz VCO

1.5 V 10-12.5 GHz integrated CMOS oscillators

On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits

A high-voltage output buffer fabricated on a 2 V CMOS technology

1999 vlsi circuits symposium rump sessions

10-100 Gb/s throughput CMOS techniques

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