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Microelectronics (ICM), 2012 24th International Conference on

Date 16-20 Dec. 2012

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  • [Title page]

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    Freely Available from IEEE
  • 2012 24th International Conference on Microelectronics (ICM) [Copyright notice]

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    Freely Available from IEEE
  • Table of contents

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  • Differential Dual Amplitude-Width PPM Coding for FSO communication systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    In this paper, a hybrid modulation scheme called DDAWPPM (Differential Dual Amplitude-Width Pulse Position Modulation) suitable with wireless optical systems has been proposed, on the basic of DPPM (Differential Pulse Position Modulation), PAM (Pulse Amplitude Modulation) and PWM (Pulse Width Modulation). The combinations (DPPM-PAM) and (DPPM-PWM) have been proposed in previous works, but the proposed DDAWPPM and beside the symbol synchronization ability, it shows more improvement in term of data rate and spectral efficiency, on the other side it shows a degradation in term of power efficiency. We present theoretical expressions of spectral efficiency, power requirements, and the normalized data rate improvement, and we present comparison results to DPPM and the hybrids PAM-DPPM and PWM-DPPM. View full abstract»

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  • Inductor implementation using CMOS current conveyor integrator for low voltage low power applications

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    A new topology of CMOS floating and ground passive coil simulation are proposed in this work. The proposed active circuits are realized using the second-generation current conveyor integrator (CCII-Int). The ground coil is modeled only using one current mode integrator. Moreover, the floating inductor is simulated by two current-mode integrators. The proposed inductor circuits are considered as low voltage and low power (LVLP) since it's used CMOS inverter as class AB transconductance circuit. The high input impedance of the CMOS inverter simplifies the op-amp design since it's loaded only by capacitive load. An LC passive butter worth filter is designed and realized using the proposed circuits. The proposed circuit is designed using the MOST parameters of the IBM 0.13µ CMOS technology. View full abstract»

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  • Virtual shared memory architecture for inter-task communication in partial reconfigurable systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    This paper presents a virtual shared memory architecture for inter-task communication in partial reconfigurable systems. The hardware tasks communicate with each other using the same content shared by physically separated Block RAMs (BRAMs). The coherence of the content is ensured by the Internal Configuration Access Port (ICAP), rather than conventional on-chip logic. The benefit of this approach resides in the flexibility of partial task reconfiguration that results from the ICAP-based synchronization mechanism, allowing hardware tasks to behave like software tasks, as they can be swapped in/out of the chip arbitrarily without any area boundary constraints. Moreover, a fast synchronization method which uses compressed bitstream is presented in this paper. The result shows significant improvements in synchronization speed at a low area overhead. View full abstract»

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  • An application of ICA-based detection to OFDM-IDMA system

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB) |  | HTML iconHTML  

    In this paper, an ICA-based blind multiuser detection approach for OFDM-IDMA system is presented. ICA is a signal processing technique that aims to detect a set of unknown mutually independent source signals from their observed mixtures without prior knowledge of the mixing coefficients. The proposed algorithm is applied as post processors attached to IDMA receiver. In this study, the performance of the proposed detector is compared to the conventional turbotype iterative OFDM-IDMA multiuser detector in which chip interleavers are the only means of user separation. Validity and performances of the described approach are demonstrated by numerical simulations based on examining the bit error rate (BER) criterion in the quasi-static Rayleigh fading channel. View full abstract»

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  • Fast and accurate analysis method of a circular patch antennas using neurospectral method

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    In this paper, fast and accurate analysis method is used to calculate the real and imaginary part of the resonant frequency of a circular patch antenna is presented. This method is based on artificial neural network (ANN), that is offered a very small computation time compared with other methods used to model this antenna such as Chew, Howell, Wolff, Demeryd, Nirun Kumprasert. The results of the real and imaginary part of the resonant frequency obtained by the ANN method for the circular antenna are in very good agreement with the experimental results available in the literature. View full abstract»

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  • Control of chaotic behaviour in buck-boost DC-DC converters

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    Chaos control is used to design a controller that is able to eliminate the chaotic behaviour of nonlinear systems that experience such phenomena. The paper describes the control of the bifurcation behaviour of a DC-DC buck-boost converter used to provide an interface between energy storage batteries and photovoltaic (PV) arrays for renewable energy sources. The paper presents a delayed feedback control scheme in a peak current-mode controlled DC-DC buck-boost converter operating in the continuous current conduction mode. MATLAB/SIMULINK simulation results show the effectiveness and robustness of the scheme. View full abstract»

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  • The thermal effect on the output conductance in AlGaN/GaN HEMT's

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (107 KB) |  | HTML iconHTML  

    The aim of this work is to study the potential offered by microwave power in the device AlGaN/GaN HEMT by studying the thermal effect and self heating on the output conductance taking into account the effects of spontaneous and piezoelectric polarization. View full abstract»

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  • A low power thermal protection topology

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    Many circuits are subject to excessive heating such as digital and power switching circuits. Overheating may cause permanent damage to the circuits and devices. In this article we present a temperature monitor the temperature variation and once a certain limit is reached, a protection mechanism could shut off the circuit operation or at least signalize for a specific operation. The circuit offers linear operation from −25 °C to +120°C, and it can be adjusted to detect any temperature in that range. The proposed circuit was developed for low voltage and low power operation, and the prototyped was designed in TSMC 0.35um technology. View full abstract»

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  • A highly efficient substitution matrix loader for pairwise sequence alignment

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    This paper presents a novel substitution matrix loader architecture for pairwise sequence alignment. The search for sequence homology using DP-based alignment matrix computation is an important tool in molecular biology. It can be implemented either by optimal or sub-optimal approaches. Both of these methods require frequent and rapid access to the amino acids probability scores for PE (Processing Element) configuration especially in a folded systolic array. Typical FPGA implementations configure look-up tables in the pipeline PEs either by using a serial configuration chain with different look-up tables or by run time reconfiguration of the same look-up table. In the former case, configuration time increases proportionally to the number of look-up tables, while the latter case suffers from the limited reconfiguration bandwidth. Therefore, in this paper, we propose a highly efficient parallel loader to optimize both time and space complexities of protein sequence alignment in folded systolic arrays, using only two configuration elements (CEs). In addition, the proposed loader enables PEs to be updated with substitution matrix scores concurrently, with the worst case configuration time of 2 × the depth of the PE's look-up table (in clock cycles). This allows for further optimization of the most time consuming alignment matrix computation through efficient scheduling of alignment matrix computation and PE configuration. Implementation results show that the proposed architecture achieves k.NPE speed-up in configuration time (where k is the folding factor and NPE is the number of PEs) compared to classical approaches, at virtually no area overhead. View full abstract»

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  • Power electronics circuit for speed control of experimental wind turbine

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    In this paper, a power electronics circuit is proposed to control the rotational speed of a wind turbine. This interface is based on two DC-DC converters, where a buck converter is used to control the speed and a boost converter is used to maintain a constant voltage for the load. The power electronics circuit is implemented on a small laboratory size wind turbine and experimentation is carried out to show its capability of speed control. View full abstract»

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  • Efficient ECC implementation architecture suitable for RFID technology

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    In this paper, we provide an investigation on the feasibility of embedding the ECC authentication service in RFID chip-set. Thus, we deal with the implementation of the most costly operation, which is the scalar point multiplication. It is also considered as the core of the security of the ECC protocols. Two architectures are studied and implemented using the Montgomery algorithm adopting the affine and projective coordinates. According to the obtained results, we show that the scalar point multiplication implementation using affine coordinates is efficient in terms of speed and area than the projective coordinates architecture. View full abstract»

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  • Influence of vertical scaling and temperature on impact-ionization effects in SiGe HBTs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    The temperature influence on impact-ionization mechanisms in advanced silicon-germanium heterojunction bipolar transistors is analyzed over the temperature range from 300 to 380 K for different technological nodes. Accurate results are obtained by performing simulations through a deterministic solver of the Boltzmann Transport Equation based on the spherical harmonics expansion of the distribution function. In particular, the impact of vertical scaling and lattice temperature on the open-base breakdown voltage BVCEO and the BVCEO×fT,PEAK product is investigated. View full abstract»

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  • Power conservation for wireless mesh network

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    Nowadays, Wireless mesh networks are being widely used as a cost-efficient means for coverage extension and backhaul relaying between IEEE 802.11 access points (APs). Recently, there has been a proliferation of application development that involves wireless access networks which is responsible for the raising in consumption and increasing demand for energy which results in the increase in carbon dioxide levels in the environment. This paper focuses mainly on different existing energy conservation methods in different networks. Several approaches are presented and discussions on the details related to energy management WMN are also presented. The classification of the layers of TCP / IP model of the largest existing approaches spent on energy conservation is treated. View full abstract»

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  • Energy monitoring system for security and power management applications

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    In this paper, we introduce an energy monitoring system composed of a mixed-signal field-programmable gate array (FPGA) device and a custom designed energy measurement circuit. The energy measurement circuit is designed as a current integrator over a fixed interval using the switched-capacitor (SC) technique. The circuit is implemented using the 65 nm CMOS technology. Simulation results show that our circuit provides energy measurement results with a precision of up to 3% for irregular input waveforms. The circuit is designed to accommodate the low sampling rate of mixed-signal FPGA devices in order to support both power management and security applications for embedded devices. View full abstract»

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  • R FMEMS circuit for space communications systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    One of the most important considerations in designing a spacecraft is weight. By reducing the weight of a spacecraft, it is possible to increase the payload, which improves agility and also reduces the launch cost [1]. Missions costs are directly proportional to its total weight, thus, the trend will be to replace bulky and heavy components of space carriers, communication and navigation platforms and of scientific payloads. RF-MEMS technology has the potential of replacing many of the mechanical and semiconductor switches used in mobile and satellite communication systems. In many cases, such RF-MEMS switches would not only reduce substantially the size and power consumption, but also promise superior performance. The paper reviews the recent development of RF MEMS switches and switch matrices. Several configurations are presented for multi-port RF-MEMS switches. View full abstract»

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  • EC-CPW fed elevated patch antenna

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    This paper presents a novel G-band (140GHz – 220GHz) integrated antenna. The antenna incorporates a newly proposed elevated center coplanar waveguide (EC-CPW) fed elevated patch antenna on a high dielectric substrate (GaAs). The proposed antenna consists of an (EC-CPW) feed line, λ/4 transformer used for matching, supporting posts, and a 5.5µm height elevated radiating patch. The antenna topology effectively creates a low-substrate dielectric constant and hence eliminates undesired substrate effects, since the antenna substrate is essentially air, the lowest possible dielectric constant. This increases the radiation efficiency, gain, and the radiation bandwidth. Close agreement between simulated and measured data have shown a good match of −20dB at 172GHz and bandwidth of 7.9GHz from 169.2GHz to 177.1GHz (return loss <−10 dB). Furthermore, the presented antenna exhibits an excellent constant broadside radiation pattern which makes it ideal for array antennas applications where directionality is an important factor avoiding pixels interferences. In addition the proposed antenna fabrication process is compatible with III-V MMICs process technology. This makes it ideal for fully integrated millimeter wave focal plane arrays applications. View full abstract»

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  • Influence of noisy channel on acoustic echo cancellation in mobile communication

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    In this paper, we investigate the influence of noisy channel on the performance of acoustic echo cancellation system. In the mobile communications, acoustic echo is mainly caused by the coupling between the loudspeaker and the microphone of the mobile device. So, an Acoustic Echo Canceller (AEC) should be used locally inside this device. This paper evaluates the performances of AEC, generally based on adaptive filtering, where the transmitted speech is encoded and decoded by AMR-WB (Adaptive Multi-Rate Wide Band) speech codec. The encoded speech is transmitted over a transmission channel modeled by AWGN (Additive White Gaussian Noise) and Rayleigh fading channel. The simulation results show the strong degradation of the AEC performances, due to the noisy channel. View full abstract»

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  • Compact modeling of long channel Double Gate MOSFET transistor

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    In this work, we present a compact modeling of long channel Double Gate MOSFET transistor with an efficient procedure to compute the mobile charge density for this model. In the first time, the static behavior of the symmetrical DG MOSFET is obtained using a relationship between charges and voltages. The model is based on the formalism EKV developed for the MOSFET bulk. In second time, to define the explicit solution of the gate charge density in weak and strong inversion, we use the Taylor series development. From that, we get an efficient algorithm that computes the gate/mobile charge density of the model with a faster computation time and without any iterative calculation. Our results are compared with the iterative calculation using the Newton-Raphson method, especially compared with 2-D numerical simulations using ATLAS-TCAD software. View full abstract»

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  • Embedded implementation of an IP-PBX /VoIP gateway

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB) |  | HTML iconHTML  

    This paper deals with an embedded IP-PBX (IPPrivate Branch exchange) /VoIP (Voice over IP) gateway, around the OpenRISC processor and an open source Asterisk PBX running on an embedded Linux kernel. In this work we leverage the Opencores reuse strategy, which provides a lower cost solution to realize a portable SoC (System on Chip) for VoIP application. In this approach both hardware and software components are Opensources. The achieved part of the system has been implemented on a Virtex5 FPGA circuit. The hardware part uses 50% of BRAM memories, 27 % of slice registers and 48% of slice LUTs, the power consumption is 4.233 W. Regarding the software part, a Linux kernel has been ported to the Virtex5 FPGA, and the network functionality of the system is successfully tested. View full abstract»

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  • Boron redistribution in strongly doped silicon thin Bi-layers gates

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    We have investigated and modeled the complex phenomenon of boron (B) redistribution process in strongly doped silicon (Si) bi-layers structure. A two stream transfer model well adapted to the particular structure of bi-layers and to the effects of strong-concentrations has been developed. This model takes into account the instantaneous kinetics of B transfer, trapping, clustering and segregation during the thermal B activation annealing. The used Si bi-layers have been obtained by low pressure chemical vapor deposition (LPCVD) method, using in-situ nitrogen-doped-silicon (NiDoS) layer and strongly B doped poly-Si (P+) layer. To avoid long redistributions, thermal annealing was carried out at relatively low-temperatures (700 and 850°C) for various times ranging between 15 minutes and 2 hours. The good adjustment of the simulated profiles with the experimental secondary ion mass spectroscopy (SIMS) profiles allowed a fundamental understanding about the instantaneous physical phenomena giving and disturbing the complex B redistribution profiles-shoulders kinetics. View full abstract»

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  • Particle swarm optimization for the identification of worst case test vectors of total-dose induced leakage current failures in ASICs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (247 KB) |  | HTML iconHTML  

    We develop a methodology for identifying worst-case test vectors necessary to detect leakage current failures in standard-cell based ASIC devices exposed to a total ionizing dose. We developed a novel search methodology based on the Particle Swarm Optimization technique. View full abstract»

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  • HOG based fast human detection

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    Objects recognition in image is one of the most difficult problems in computer vision. It is also an important step for the implementation of several existing applications that require high-level image interpretation. Therefore, there is a growing interest in this research area during the last years. In this paper, we present an algorithm for human detection and recognition in real-time, from images taken by a CCD camera mounted on a car-like mobile robot. The proposed technique is based on Histograms of Oriented Gradient (HOG) and SVM classifier. The implementation of our detector has provided good results, and can be used in robotics tasks. View full abstract»

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