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High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International

Date 9-10 Nov. 2012

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Displaying Results 1 - 25 of 29
  • Chairs welcome message

    Publication Year: 2012 , Page(s): 1
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  • Organizing committee

    Publication Year: 2012 , Page(s): 1
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  • Table of contents

    Publication Year: 2012 , Page(s): 1 - 3
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  • Author index

    Publication Year: 2012 , Page(s): 1 - 3
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  • [Copyright notice]

    Publication Year: 2012 , Page(s): 1
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  • Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies

    Publication Year: 2012 , Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (589 KB) |  | HTML iconHTML  

    We propose two approaches to significantly boost the power of sequential equivalence checking: (1) In contrast with invariants involving only two or three signals, we introduce a novel multisignal invariant generation technique that is scalable to large circuits; (2) We utilize static and dynamic filters to reduce the number of potential inductive invariants that need to be proved to further reduc... View full abstract»

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  • Behavior Driven Development for circuit design and verification

    Publication Year: 2012 , Page(s): 9 - 16
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (509 KB) |  | HTML iconHTML  

    The design of hardware systems is a challenging and erroneous task where about 70% of the effort in designing these systems is spent on verification. In general, testing and verification are usually tasks that are being applied as a post-process to the implementation. In this paper, we propose a new design flow based on Behavior Driven Development (BDD), an agile technique for the development of s... View full abstract»

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  • Using decision diagrams to compactly represent the state space for explicit model checking

    Publication Year: 2012 , Page(s): 17 - 24
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1222 KB) |  | HTML iconHTML  

    The enormous number of states reachable during explicit model checking is the main bottleneck for scalability. This paper presents approaches of using decision diagrams to represent very large state space compactly and efficiently. This is possible for asynchronous systems as two system states connected by a transition often share many same local portions. Using decision diagrams can significantly... View full abstract»

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  • Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics

    Publication Year: 2012 , Page(s): 25 - 32
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1277 KB) |  | HTML iconHTML  

    In the multi-core era, ensuring deadlock freedom of communication fabrics is an important challenge. Intel proposed xMAS, a microarchitecture description language (MaDL), to support the formal modelling and verification of communication fabrics. The xMAS language is restricted to eight basic primitives. Using this restriction, an efficient deadlock detection technique has been defined. This techni... View full abstract»

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  • Automatic generation of Verilog bus transactors from natural language protocol specifications

    Publication Year: 2012 , Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (469 KB) |  | HTML iconHTML  

    We present an approach to analyze natural language protocol specifications to generate Verilog bus transactors. We present a set of transaction concepts which are used, in text and formal models, to describe the behavior of transactions in a protocol. We employ semantic parsing to identify these transaction concepts in the natural language specification. The transaction concepts are translated int... View full abstract»

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  • Single-source hardware modeling of different abstraction levels with State Charts

    Publication Year: 2012 , Page(s): 41 - 48
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (538 KB) |  | HTML iconHTML  

    This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a ... View full abstract»

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  • Using haloes in mixed-signal assertion based verification

    Publication Year: 2012 , Page(s): 49 - 55
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    We develop an assertion based verification solution for analog mixed-signal designs. We introduce the halo concept for analog signals to express them with their tolerance and variation values in assertions. The halo of a signal provides a relaxation over the signal and it defines an effective region for that signal which can be used in assertion based verification. Using haloes for analog signals ... View full abstract»

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  • A formal method to improve SystemVerilog functional coverage

    Publication Year: 2012 , Page(s): 56 - 63
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1781 KB) |  | HTML iconHTML  

    Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce d... View full abstract»

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  • A functional test generation technique for RTL datapaths

    Publication Year: 2012 , Page(s): 64 - 70
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault coverage it is essential to symbolically simulate all possible execution paths, we have come up with a case splitting mechanism which makes use of pa... View full abstract»

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  • Constrained signal selection for post-silicon validation

    Publication Year: 2012 , Page(s): 71 - 75
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    Limited signal observability is a major concern during post-silicon validation. On-chip trace buffers store a small number of signal states every cycle. Existing signal selection techniques are designed to select a set of signals based on the trace buffer width. In a real-life scenario, it is reasonable that a designer has determined some important signals that must be traced. In this paper, we st... View full abstract»

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  • The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

    Publication Year: 2012 , Page(s): 76 - 83
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (676 KB) |  | HTML iconHTML  

    Modern embedded systems require a tight integration among several heterogeneous components including digital and analog HW, as well as HW-dependent SW. In literature there is a lack of a complete approach, allowing reuse and at the same time supporting correct integration of heterogeneous components. Indeed, traditional approaches rely either on homogeneous top-down methodologies (that do not allo... View full abstract»

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  • Monitoring distributed reactive systems

    Publication Year: 2012 , Page(s): 84 - 91
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (607 KB) |  | HTML iconHTML  

    Recent results on the desynchronization of synchronous systems introduced the subclass of so-called endo/isochronous systems. Since the modules of these systems can derive their own local clocks from their inputs, they can be implemented as asynchronous components without inefficient synchronizations. Runtime verification has a similar problem since one has to add a monitor to an existing system w... View full abstract»

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  • Embedded system verification through constraint-based scheduling

    Publication Year: 2012 , Page(s): 92 - 95
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (514 KB) |  | HTML iconHTML  

    Multiprocessor System-on-Chip (MPSoC) verification has become one of the main bottlenecks in the design process of embedded systems. Proving the correctness of a design efficiently is of extreme importance to reduce cost and time-to-market. Simulation is a common verification method, but complex systems usually require long simulation times. This work introduces Constraint Programming (CP) as a po... View full abstract»

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  • Accurate profiling of oracles for self-checking time-constrained embedded software

    Publication Year: 2012 , Page(s): 96 - 99
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    One way to ensure the correct execution of embedded software is to keep debugging and testing even after shipping of the application, complemented with recovery/restart operations. In this context, the oracles, i.e., assertions and checkers, that have been widely used in the development process for design validation, can be deployed again in the final product. The application will use the oracles ... View full abstract»

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  • Post-silicon verification and debugging with control flow traces and patchable hardware

    Publication Year: 2012 , Page(s): 100 - 107
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    In this paper we show three methods for postsilicon verification and debugging with control-flow analysis. By concentrating on control flows of SoC behavior, abstracted analysis can be applied and much significantly long time spans can be examined. The first method introduces monitoring methods of communications or transactions among cores inside SoCs. From the monitoring results, control sequence... View full abstract»

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  • On-chip stimuli generation for post-silicon validation

    Publication Year: 2012 , Page(s): 108 - 109
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation of the events of interest are the real concern. This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into pos... View full abstract»

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  • Emulation in post-silicon validation: It's not just for functionality anymore

    Publication Year: 2012 , Page(s): 110 - 117
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (959 KB) |  | HTML iconHTML  

    FPGA-based emulation has emerged as an important tool in the overall validation process for an increasing number of large integrated circuits. Emulation gives the ability to validate a design using long-running, realistic tests, which are infeasible to perform using simulation. Traditionally, however, FPGA-based emulation has been used to validate only the functional behavior of an integrated circ... View full abstract»

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  • Eliminating race conditions in system-level models by using parallel simulation infrastructure

    Publication Year: 2012 , Page(s): 118 - 123
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1309 KB) |  | HTML iconHTML  

    For a top-down system design flow, a well-written specification model of an embedded system is crucial for its successful design and implementation. However, the task of writing a correct system-level model is difficult, as it involves, among other tasks, the insertion of parallelism. In this paper, we focus on ensuring model correctness under parallel execution. In particular, the model must be f... View full abstract»

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  • Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators

    Publication Year: 2012 , Page(s): 124 - 131
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (381 KB) |  | HTML iconHTML  

    Simulators are used to aid the design of computer systems. Together with the computational power of computer systems, the demands towards their simulators are growing regarding speed, flexibility, as well as the predictability of their behavior. To increase simulation speed, simulation models are abstracted and simulated in parallel. To reduce simulator development time and to provide the greatest... View full abstract»

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  • Accelerating SystemC simulations using GPUs

    Publication Year: 2012 , Page(s): 132 - 139
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1365 KB) |  | HTML iconHTML  

    Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing ... View full abstract»

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