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Date 19-22 Nov. 2012

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Displaying Results 1 - 25 of 89
  • [Cover art]

    Publication Year: 2012, Page(s): C4
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  • [Title page i]

    Publication Year: 2012, Page(s): i
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  • [Title page iii]

    Publication Year: 2012, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2012, Page(s): iv
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  • Table of contents

    Publication Year: 2012, Page(s):v - xii
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  • Foreword

    Publication Year: 2012, Page(s): xii
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  • Organizing Committee

    Publication Year: 2012, Page(s): xiii
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  • Program Committee

    Publication Year: 2012, Page(s):xiv - xv
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  • Reviewers

    Publication Year: 2012, Page(s): xvi
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  • Steering Committee

    Publication Year: 2012, Page(s): xvii
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  • Tutorials

    Publication Year: 2012, Page(s):xviii - xix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (106 KB) | HTML iconHTML

    This tutorial discusses the following:Beyond DFT: The Convergence of DFM, Variability, Yield, Diagnosis and Reliability; and Power-Aware Testing and Test Strategies for Low Power Devices. View full abstract»

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  • [Keynote Addresses - 2 abstracts]

    Publication Year: 2012, Page(s):xx - xxi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (121 KB)

    Provides an abstract for each of the two keynote presentations and a brief professional biography of each presenter. View full abstract»

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  • Invited talks [2 abstracts]

    Publication Year: 2012, Page(s):xxii - xxv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB)

    Provides an abstract for each of the two invited talk presentations and a brief professional biography of each presenter. View full abstract»

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  • ATS 2013 Call for Papers

    Publication Year: 2012, Page(s): xxvi
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  • An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms

    Publication Year: 2012, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (125 KB) | HTML iconHTML

    Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-spe... View full abstract»

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  • LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits

    Publication Year: 2012, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB) | HTML iconHTML

    With a large focus on test data size and fitting into tester's capabilities, sometimes the focus of field testing is pushed to the side. There is an emerging market in automotive design where greater emphasis is being placed on the need for field testing of the digital logic. Tried and true mechanical systems are being replaced by digitally controlled logic. This path is being pursued by automotiv... View full abstract»

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  • Portable/Desktop Testing Solution for Engineering with Cloud

    Publication Year: 2012, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB) | HTML iconHTML

    This papar presents new concept of testing which provided software from cloud at internet. Entire concept is designed for engineering at testing lab, office, and class room, etc. View full abstract»

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  • Characteristics Variability Evaluation of Actual LSI Transistors with Nanoprobing

    Publication Year: 2012, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (114 KB) | HTML iconHTML

    In this paper, we propose an evaluation method of characteristics variability of MOS transistors in an actual circuit with nanoprobing. Based on the evaluation of a huge scale test structure, we verified that the nanoprobing had ability for varia-bility evaluations. And the evaluation of SRAM cells in an actual LSI die, we confirmed that a variation of threshold voltage is normal distribution. View full abstract»

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  • F-matrix (ABCD-matrix) Circuit Simulation Built in IC Test Program

    Publication Year: 2012, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB) | HTML iconHTML

    F-matrix is utilized to simulate signal paths with introducing the F-matrix type and its multiplication. It is applied to generate signals for AWG and compensate digitized signals. View full abstract»

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  • Addressing Test Challenges in Advanced Technology Nodes

    Publication Year: 2012, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (49 KB) | HTML iconHTML

    As process technologies continue to shrink and design complexity grows, today's designs present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity and new defects at small geometries. The designs are larger and using multiple processor cores in SoCs to enable the next generation of mobile internet devices. Each core contains... View full abstract»

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  • Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns

    Publication Year: 2012, Page(s):7 - 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    In this paper we present a methodology to accurately diagnose cell internal defects when test patterns with multiple capture cycles are used. The multi-cycle test patterns can lead to more possible excitation conditions such that the existing extraction methods become less accurate. In addition, the realistic cell internal defects may produce different faulty values at different capture cycles, or... View full abstract»

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  • Automated Post-Silicon Debugging of Failing Speedpaths

    Publication Year: 2012, Page(s):13 - 18
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (709 KB) | HTML iconHTML

    Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain.... View full abstract»

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  • SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions

    Publication Year: 2012, Page(s):19 - 24
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB) | HTML iconHTML

    Introducing partial programmability in circuits by replacing some gates with look up tables (LUTs) can be an effective way to improve post-silicon or in-field rectification and debugging. Although finding configurations of LUTs that can correct the circuits can be formulated as a QBF problem, solving it by state-of-the-art QBF solvers is still a hard problem for large circuits and many LUTs. In th... View full abstract»

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  • A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips

    Publication Year: 2012, Page(s):25 - 30
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB) | HTML iconHTML

    Digital Micro fluidic biochips have been developed as a promising platform for Lab-on-chip systems that manipulate individual droplet of chemicals on a 2D planar array of electrodes. Due to the significance of the correctness of the results -- fault tolerance and dependability becomes a major issue for operation of these devices. Therefore, such devices are required to be tested frequently both of... View full abstract»

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  • TSV Stress-Aware ATPG for 3D Stacked ICs

    Publication Year: 2012, Page(s):31 - 36
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1061 KB) | HTML iconHTML

    Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-f... View full abstract»

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