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Embedded Computer Systems (SAMOS), 2012 International Conference on

Date 16-19 July 2012

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Displaying Results 1 - 25 of 62
  • [Front cover]

    Publication Year: 2012 , Page(s): c1
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  • [Title page]

    Publication Year: 2012 , Page(s): 1
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  • Proceedings 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) [Copyright notice]

    Publication Year: 2012 , Page(s): 1
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  • IC-SAMOS organization

    Publication Year: 2012 , Page(s): 1 - 4
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  • Preface

    Publication Year: 2012 , Page(s): 1
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  • Table of contents

    Publication Year: 2012 , Page(s): 1 - 5
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  • The homogeneity of architecture in a heterogeneous world

    Publication Year: 2012 , Page(s): i
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (99 KB) |  | HTML iconHTML  

    Summary form only given. It has long been accepted within embedded computing that using a heterogeneous core focused to a specific task can deliver improved performance and subsequent improved power efficiency. The challenge has always been how can the software programmer integrate this hardware diversity as workloads become generalized or often unknown at design time? Using library abstraction pe... View full abstract»

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  • It's about time

    Publication Year: 2012 , Page(s): ii
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    Summary form only given. All widely used software abstractions lack temporal semantics. The notion of correct execution of a program written in every widely-used programming language and in nearly every processor instruction-set today does not depend on the timing of the execution. Computer architects exploit the fact that timing is irrelevant to correctness with aggressive performance-enhancing t... View full abstract»

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  • Maximum performance computing for exascale applications

    Publication Year: 2012 , Page(s): iii
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (602 KB)  

    Summary form only given. Ever since Fermi, Pasta and Ulam conducted the first fundamentally important numerical experiments in 1953, science has been driven by the progress of available computational capability. In particular, computational quantum chemistry and computational quantum physics depend on ever increasing amounts of computation. However, due to power density limitations at the chip we ... View full abstract»

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  • Just-in-Time Verification in ADL-based processor design

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (674 KB) |  | HTML iconHTML  

    A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specifica... View full abstract»

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  • Interleaving methods for hybrid system-level MPSoC design space exploration

    Publication Year: 2012 , Page(s): 7 - 14
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (555 KB) |  | HTML iconHTML  

    System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. Simulatio... View full abstract»

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  • A template-based methodology for efficient microprocessor and FPGA accelerator co-design

    Publication Year: 2012 , Page(s): 15 - 22
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1082 KB) |  | HTML iconHTML  

    Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose ... View full abstract»

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  • Using OpenMP superscalar for parallelization of embedded and consumer applications

    Publication Year: 2012 , Page(s): 23 - 32
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (754 KB) |  | HTML iconHTML  

    In the past years, research and industry have introduced several parallel programming models to simplify the development of parallel applications. A popular class among these models are task-based programming models which proclaim ease-of-use, portability, and high performance. A novel model in this class, OpenMP Superscalar, combines advanced features such as automated runtime dependency resoluti... View full abstract»

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  • Virtual prototyping for efficient multi-core ECU development of driver assistance systems

    Publication Year: 2012 , Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (845 KB) |  | HTML iconHTML  

    In recent years, road vehicles have experienced an enormous increase in driver assistance systems such as traffic sign recognition, lane departure warning, and pedestrian detection. Cost-efficient development of electronic control units (ECUs) for these systems is a complex challenge. The demand for shortened time to market makes the development even more challenging and thus demands efficient des... View full abstract»

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  • System modeling and multicore simulation using transactions

    Publication Year: 2012 , Page(s): 41 - 50
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (797 KB) |  | HTML iconHTML  

    With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become a necessity. This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to develop a system-level modeling and parall... View full abstract»

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  • HNOCS: Modular open-source simulator for Heterogeneous NoCs

    Publication Year: 2012 , Page(s): 51 - 57
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1113 KB) |  | HTML iconHTML  

    We present HNOCS (Heterogeneous Network-on-Chip Simulator), an open-source NoC simulator based on OMNeT++. To the best of our knowledge, HNOCS is the first simulator to support modeling of heterogeneous NoCs with variable link capacities and number of VCs per unidirectional port. The HNOCS simulation platform provides an open-source, modular, scalable, extendible and fully parameterizable framewor... View full abstract»

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  • BADCO: Behavioral Application-Dependent Superscalar Core model

    Publication Year: 2012 , Page(s): 58 - 67
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    Microarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approxim... View full abstract»

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  • An application-specific Network-on-Chip for control architectures in RF transceivers

    Publication Year: 2012 , Page(s): 68 - 75
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1275 KB) |  | HTML iconHTML  

    This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart transceivers supporting multi-mode standards, led to new and complex SoC (System-on-Chip) designs. These designs are defined by a distributed controlling concept using several proces... View full abstract»

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  • A framework for efficient cache resizing

    Publication Year: 2012 , Page(s): 76 - 85
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1066 KB) |  | HTML iconHTML  

    We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the running applications. Our framework enables smooth scaling (i.e., resizing) of the on-chip caches targeting both performance and power efficiency. In contrast to previous approaches, the resizing decisions in our framework are not tainted by transient events (e.g., misses) tha... View full abstract»

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  • OSR-Lite: Fast and deadlock-free NoC reconfiguration framework

    Publication Year: 2012 , Page(s): 86 - 95
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1494 KB) |  | HTML iconHTML  

    Current and future on-chip networks will feature an enhanced degree of reconfigurability. Power management and virtualization strategies as well as the need to survive to the progressive onset of wear-out faults are root causes for that. In all these cases, a non-intrusive and efficient reconfiguration method is needed to allow the network to function uninterruptedly over the course of the reconfi... View full abstract»

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  • A tightly-coupled multi-core cluster with shared-memory HW accelerators

    Publication Year: 2012 , Page(s): 96 - 103
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    Tightly coupling hardware accelerators with processors is a well-known approach for boosting the efficiency of MPSoC platforms. The key design challenges in this area are: (i) streamlining accelerator definition and instantiation and (ii) developing architectural templates and run-time techniques for minimizing the cost of communication and synchronization between processors and accelerators. In t... View full abstract»

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  • Architecture-level fault-tolerance for biomedical implants

    Publication Year: 2012 , Page(s): 104 - 112
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1190 KB) |  | HTML iconHTML  

    In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants. The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance techniques. The proposed architecture allows run-time tradeoffs between performance and fault tol... View full abstract»

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  • Reconfigurable miniature sensor nodes for condition monitoring

    Publication Year: 2012 , Page(s): 113 - 119
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (877 KB) |  | HTML iconHTML  

    The wireless sensor networks are being deployed at escalating rate for various application fields. The ever growing number of application areas requires a diverse set of algorithms with disparate processing needs. The wireless sensor networks also need to adapt to the prevailing energy conditions and processing requirements. The preceding reasons rule out the use of a single fixed design. Instead ... View full abstract»

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  • Counting stream registers: An efficient and effective snoop filter architecture

    Publication Year: 2012 , Page(s): 120 - 127
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1281 KB) |  | HTML iconHTML  

    We introduce a counting stream register snoop filter, which improves the performance of existing snoop filters based on stream registers. Over time, this class of snoop filters loses the ability to filter memory addresses that have been loaded, and then evicted, from the caches that are filtered; they include cache wrap detection logic, which resets the filter whenever the contents of the cache ha... View full abstract»

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  • Design space exploration in application-specific hardware synthesis for multiple communicating nested loops

    Publication Year: 2012 , Page(s): 128 - 135
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1243 KB) |  | HTML iconHTML  

    Application specific MPSoCs are often used to implement high-performance data-intensive applications. MPSoC design requires a rapid and efficient exploration of the hardware architecture possibilities to adequately orchestrate the data distribution and architecture of parallel MPSoC computing resources. Behavioral specifications of data-intensive applications are usually given in the form of a loo... View full abstract»

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