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Test Conference (ITC), 2012 IEEE International

Date 5-8 Nov. 2012

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Displaying Results 1 - 25 of 83
  • [Front cover]

    Page(s): 1
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    Freely Available from IEEE
  • [Title page]

    Page(s): 1
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): ii
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    Freely Available from IEEE
  • Table of contents

    Page(s): iii - xiii
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    Freely Available from IEEE
  • Welcome message

    Page(s): 1
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  • Steering committee

    Page(s): 2 - 3
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    Freely Available from IEEE
  • Awards

    Page(s): 4
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    Freely Available from IEEE
  • Technical program committee

    Page(s): 5
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    Freely Available from IEEE
  • ITC technical paper evaluation and selection process

    Page(s): 6
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    Freely Available from IEEE
  • 2013 call for papers

    Page(s): 7
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    Freely Available from IEEE
  • Keynote address

    Page(s): 8 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (93 KB)  

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • TTTC: Test technology technical council

    Page(s): 11 - 12
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    Freely Available from IEEE
  • Technical paper reviewers

    Page(s): 13 - 18
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  • Cell-aware Production test results from a 32-nm notebook processor

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1262 KB) |  | HTML iconHTML  

    This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part. View full abstract»

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  • The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (210 KB) |  | HTML iconHTML  

    The DFT and test challenges faced, and the solutions applied, to the Cortex-A15 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT flow that addresses multiple identical CPUs that will ultimately end up in many different design and test environments. We describe work done with EDA vendors to ensure that all mutual customers are able to implement this flow. In addition, this paper discusses the use of the ARM MBIST standardized interface in conjunction with a 3rd party MBIST controller for the first time. We collaborated closely with the 3rd party tool company and met all of the challenges to get this first time flow and tool capability working successfully on silicon. View full abstract»

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  • A dynamic programming solution for optimizing test delivery in multicore SOCs

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization. Test-time minimization for grid-based NOCs is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. The proposed method yields high-quality results that are comparable to integer linear programming (ILP), but unlike ILP, it is scalable to large SOCs with many cores. We present results on synthetic NOC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores. View full abstract»

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  • On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

    Page(s): 1 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations and layout dependent effects. On-die instrumentation (ODI) is an effective means to alleviate many of the challenges, as well as characterize and margin performance. This paper covers two of the ODI techniques used in the design of a wide range 28nm, 28Gbps transceiver. View full abstract»

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  • A digital method for phase noise measurement

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    To reduce the test costs of phase noise measurements, we use all-digital methods to detect sinusoidal phase noise components while reducing the need for computation intensive FFT. View full abstract»

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  • Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB)  

    In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted signals inside the bandwidth of interest. The generated spectral images are used as the primary output of the proposed system. The waveform synthesizer is capable of digitally controlling the phase noise characteristics of the output signal in the high-order Nyquist zones. In addition, it utilizes relatively low-cost off-the-shelf integrated circuits (ICs) for multi-GHz signal generation. In hardware validation, dual DACs operating at 2.5Gb/s (effective Nyquist rate of 5 Gb/s) are used to generate a signal centered at 3.2GHz (corresponding to a Nyquist rate of 6.4 GHz). In addition, controlled phase noise generation is demonstrated. View full abstract»

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  • On efficient silicon debug with flexible trace interconnection fabric

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of “key” signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug run. However, both kinds of trace interconnection fabrics have limitations. On one hand, with MUX-based fabric, the visibility of the circuit is limited and it requires many debug runs to locate errors. On the other hand, with XOR-based fabric, typically clean “golden vectors” (i.e, without unknown bits) are required so that signatures are not corrupted. In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique. View full abstract»

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  • Adaptive test selection for post-silicon timing validation: A data mining approach

    Page(s): 1 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2255 KB) |  | HTML iconHTML  

    Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow via bug root-cause analysis. However, the value of this silicon data for helping further improvement of the post-silicon validation process has been largely overlooked. In this paper, we propose an adaptive test selection method to progressively tune the validation plan using knowledge automatically mined from the bug sightings during post-silicon validation. Experimental results demonstrate that the proposed fault-model-free data mining approach can prioritize those tests capable of uncovering more silicon timing errors, resulting in significant reduction of validation time and effort. View full abstract»

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  • In-system constrained-random stimuli generation for post-silicon validation

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (667 KB) |  | HTML iconHTML  

    When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment. View full abstract»

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  • Driver sharing challenges for DDR4 high-volume testing with ATE

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB) |  | HTML iconHTML  

    The need for larger and faster memories has been a constant requirement in the last decades together with keeping memory costs constant or lower. This presents a significant challenge for cost effective memory testing, not only because of the increased data rates but also the pressure to keep memory testing costs down. This paper addresses one of these challenges, which is the development of driver-sharing designs to allow the development of DDR test solutions with a high number of sites. This paper will describe in detail the challenges that high-volume ATE testing of DDR4 presents in regard to driver sharing, allowing the test engineer to better grasp the problems associated with DDR4 high-volume ATE testing. View full abstract»

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  • 8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability

    Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2073 KB) |  | HTML iconHTML  

    In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system. View full abstract»

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  • Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter

    Page(s): 1 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2483 KB) |  | HTML iconHTML  

    A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on a cycle-to-cycle basis. The period (frequency) can be changed on a bit-by-bit basis. Real-time algorithmic calculation of timing values is accomplished using a pipelined FPGA controller so that highly complex timing sequences can be synthesized. The ATG generates timing edges according to the FPGA calculations, and combines these with serialized digital “pattern” data to create the desired signal waveforms. A prototype supports ~10ps resolution and achieves approximately +/-20ps accuracy (including 6σ random jitter). Its maximum sustainable data rate is 3.2Gbps (non-multiplexed) and 6.4Gbps (multiplexed). Bursts patterns up to 10.0Gbps are also demonstrated. Minimum pulse-width is ~70ps. View full abstract»

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