By Topic

2012 IEEE International Test Conference

Date 5-8 Nov. 2012

Filter Results

Displaying Results 1 - 25 of 83
  • [Front cover]

    Publication Year: 2012, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (203 KB)
    Freely Available from IEEE
  • [Title page]

    Publication Year: 2012, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (56 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2012, Page(s): ii
    Request permission for commercial reuse | PDF file iconPDF (33 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2012, Page(s):iii - xiii
    Request permission for commercial reuse | PDF file iconPDF (102 KB)
    Freely Available from IEEE
  • Welcome message

    Publication Year: 2012, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (66 KB) | HTML iconHTML
    Freely Available from IEEE
  • Steering committee

    Publication Year: 2012, Page(s):2 - 3
    Request permission for commercial reuse | PDF file iconPDF (125 KB)
    Freely Available from IEEE
  • Awards

    Publication Year: 2012, Page(s): 4
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • Technical program committee

    Publication Year: 2012, Page(s): 5
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • ITC technical paper evaluation and selection process

    Publication Year: 2012, Page(s): 6
    Request permission for commercial reuse | PDF file iconPDF (63 KB)
    Freely Available from IEEE
  • 2013 call for papers

    Publication Year: 2012, Page(s): 7
    Request permission for commercial reuse | PDF file iconPDF (75 KB)
    Freely Available from IEEE
  • Keynote address

    Publication Year: 2012, Page(s):8 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (93 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TTTC: Test technology technical council

    Publication Year: 2012, Page(s):11 - 12
    Request permission for commercial reuse | PDF file iconPDF (72 KB)
    Freely Available from IEEE
  • Technical paper reviewers

    Publication Year: 2012, Page(s):13 - 18
    Request permission for commercial reuse | PDF file iconPDF (69 KB)
    Freely Available from IEEE
  • Cell-aware Production test results from a 32-nm notebook processor

    Publication Year: 2012, Page(s):1 - 9
    Cited by:  Papers (15)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1262 KB) | HTML iconHTML

    This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor

    Publication Year: 2012, Page(s):1 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    The DFT and test challenges faced, and the solutions applied, to the Cortex-A15 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT flow that addresses multiple identical CPUs that will ultimately end up in many different design and test environments. We describe work done with EDA vendors to ensure that all mutual c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A dynamic programming solution for optimizing test delivery in multicore SOCs

    Publication Year: 2012, Page(s):1 - 10
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB) | HTML iconHTML

    We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

    Publication Year: 2012, Page(s):1 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (515 KB) | HTML iconHTML

    Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations and layout dependent effects. On-die instrumentation (ODI) is an effective means to alleviate many of the challenges, as well as characterize and margi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A digital method for phase noise measurement

    Publication Year: 2012, Page(s):1 - 10
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    To reduce the test costs of phase noise measurements, we use all-digital methods to detect sinusoidal phase noise components while reducing the need for computation intensive FFT. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters

    Publication Year: 2012, Page(s):1 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On efficient silicon debug with flexible trace interconnection fabric

    Publication Year: 2012, Page(s):1 - 9
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (361 KB) | HTML iconHTML

    Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of “key” signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adaptive test selection for post-silicon timing validation: A data mining approach

    Publication Year: 2012, Page(s):1 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2255 KB) | HTML iconHTML

    Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow via bug root-cause analysis. However, the value of this silicon data for helping further improvement of the post-silicon validation process has... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • In-system constrained-random stimuli generation for post-silicon validation

    Publication Year: 2012, Page(s):1 - 10
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (667 KB) | HTML iconHTML

    When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Driver sharing challenges for DDR4 high-volume testing with ATE

    Publication Year: 2012, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB) | HTML iconHTML

    The need for larger and faster memories has been a constant requirement in the last decades together with keeping memory costs constant or lower. This presents a significant challenge for cost effective memory testing, not only because of the increased data rates but also the pressure to keep memory testing costs down. This paper addresses one of these challenges, which is the development of drive... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability

    Publication Year: 2012, Page(s):1 - 9
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2073 KB) | HTML iconHTML

    In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm × 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a singl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter

    Publication Year: 2012, Page(s):1 - 11
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2483 KB) | HTML iconHTML

    A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.