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SOC Conference (SOCC), 2012 IEEE International

Date 12-14 Sept. 2012

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Displaying Results 1 - 25 of 84
  • [Front matter]

    Publication Year: 2012 , Page(s): 1 - 3
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  • Message from conference general chair

    Publication Year: 2012 , Page(s): 1
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  • Message from program chairs

    Publication Year: 2012 , Page(s): 1 - 2
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  • Program at a glance

    Publication Year: 2012 , Page(s): 1
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  • Committee

    Publication Year: 2012 , Page(s): 1 - 2
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  • List of reviewers

    Publication Year: 2012 , Page(s): 1
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  • Table of contents

    Publication Year: 2012 , Page(s): 1 - 8
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  • Author index

    Publication Year: 2012 , Page(s): 1 - 3
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  • Keynote speaker: Driving innovation in the "post-silicon" world

    Publication Year: 2012 , Page(s): 1 - 2
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  • Plenary speaker: Low power solutions for a smarter future

    Publication Year: 2012 , Page(s): 3
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  • Plenary speaker: Era of SoCs: What is next?

    Publication Year: 2012 , Page(s): 4
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  • An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation

    Publication Year: 2012 , Page(s): 5 - 10
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (113 KB) |  | HTML iconHTML  

    A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Conventional level converters fail to work in sub-threshold region due to the pull-down devices and the pull-up devices operate in sub-threshold and super-threshold region respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), and stack leakage reduction techniques, the proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance. Also, the reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. We also propose a dual edge-triggered explicit-pulsed level-converting flip flop (LCFF) concept combining a DCVSPG latch and our level converter. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter has a propagation delay of 52ns and a power dissipation of 21nW when the input voltage is 150mV. View full abstract»

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  • An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor

    Publication Year: 2012 , Page(s): 11 - 14
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (726 KB) |  | HTML iconHTML  

    We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm2. To suppress the AC voltage drop due to large load transient (LLT), we developed a LLT control method using dynamic sampling clock frequency scaling scheme. The measurement results show that the AC voltage drop can be suppressed to 50%. The peak efficiency is 99% at 250 mA. View full abstract»

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  • A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation

    Publication Year: 2012 , Page(s): 15 - 20
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (573 KB) |  | HTML iconHTML  

    Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5% performance loss. View full abstract»

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  • Variation-and-aging aware low power embedded SRAM for multimedia applications

    Publication Year: 2012 , Page(s): 21 - 26
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    This paper presents a low power embedded SRAM memory design for MPEG-4 video processors. Considering both of the process variation and aging effect, the proposed design adopts an optimal high voltage for spatial voltage scaling to achieve high power efficiency. Simulations in FreePDK 45nm CMOS technology show that our proposed technique can achieve 85%, 90%, and 79% reduction in write power, read power, and leakage current, respectively, with graceful degradation (~5.6%) in video quality, as compared to conventional SRAM design. View full abstract»

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  • pbCAM: Probabilistically-banked Content Addressable Memory

    Publication Year: 2012 , Page(s): 27 - 32
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB) |  | HTML iconHTML  

    Content Addressable Memories find wide use in network routers and certain image processing applications. However, their use is limited due to their high power demand resulting from their high activity factor. A banked CAM, on the other hand, partitions the entire CAM into smaller banks to cut down on excessive searches, while it may reduce the effective CAM size when the data entries are unevenly distributed. A new banked CAM design is introduced in this paper which achieves significant energy and power savings through the use of Bloom Filters by effectively decoupling data elements from their bank index. Simulation results show energy savings of nearly an order of magnitude. View full abstract»

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  • “Free” Razor: A novel adaptive voltage scaling low power technique for data path SoC designs

    Publication Year: 2012 , Page(s): 33 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB) |  | HTML iconHTML  

    This paper proposes a novel adaptive voltage scaling low power design methodology for large System on Chip (SoC) that demands constant data throughput. The proposed technique scales the supply voltage to the SoC based on operating conditions and bit error rate (BER) margin available in a system. It allows occasional timing errors in the circuit and relies on a forward error correction (FEC) that exists in the system to correct the errors. As a result, the proposed technique requires no hardware overhead but yields significant power savings. More importantly, it does not require any circuit modification based on place and route, thus easy to implement and has no impact on time to market. The new technique has been implemented in a complex telecom SoC design and silicon measurement shows power savings up to 46%. View full abstract»

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  • ADPLL variables determinations based on phase noise, spur and locking time

    Publication Year: 2012 , Page(s): 39 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3375 KB) |  | HTML iconHTML  

    This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables in ADPLL can be properly selected to meet the phase noise, spur and locking time requirements. For model validation, we collect the ADPLL circuit designs published in the recent literature and perform model analysis. The analysis results and hardware measurements show good agreements. View full abstract»

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  • A novel digital loop filter architecture for bang-bang ADPLL

    Publication Year: 2012 , Page(s): 45 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    Bang-Bang Phase Locked Loops (BB-PLLs) exhibit a nonlinear response that is dependent on the magnitude of the phase error. This paper presents a novel Digital Loop Filter (DLF) with coefficients that adapt to the relative magnitude of the phase error, and hence, enhances system linearity. An All-Digital BB-PLL (BB-ADPLL) that incorporates the proposed DLF is implemented using 32nm technology. AMS simulations are used to demonstrate the impact of the proposed DLF on the system linearity. Furthermore, theoretical analysis indicates 75% enhancement in the linearity of the proposed system compared to conventional DLFs. View full abstract»

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  • A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-hold

    Publication Year: 2012 , Page(s): 51 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1896 KB) |  | HTML iconHTML  

    A High-Speed Analog-to-Digital Converter was implemented utilizing a novel distributed sample-and-hold, output offset storage comparator. The number of storage capacitors is minimized by use of one offset cancellation stage per two amplifiers, a technique used for the first time, in our knowledge. View full abstract»

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  • A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

    Publication Year: 2012 , Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1752 KB) |  | HTML iconHTML  

    In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 231-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply. View full abstract»

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  • Gray-level image recognition on a dynamically reconfigurable vision architecture

    Publication Year: 2012 , Page(s): 61 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (966 KB)  

    Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such system requires many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Realizing such high-speed real-time image recognition operation is difficflt because of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigurable vision architecture that can recognize binarized images has been presented. However, to date, no dynamically reconfigurable vision architecture that can recognize gray-level images has ever been presented. Therefore, this paper presents experimentation related to a more advanced dynamically reconfigurable vision architecture that can recognize gray-level images. View full abstract»

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  • A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs

    Publication Year: 2012 , Page(s): 66 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB) |  | HTML iconHTML  

    SoCs yield in nanometer CMOS technologies is largely governed by SRAM reliability. Sense amplifier (SA) is a crucial component in an SRAM macro. Mismatch variation in conventional SAs can cause SRAM read failure. The problem becomes worst when the SRAM array operates at low voltage. In this work we propose a timing-insensitive SA scheme featuring read-assist and write-back mechanisms. Carried out Monte Carlo simulations on a 500 mV typical 6T-SRAM column confirm the robustness of the proposed SA against up to 5σ mismatch variations. Owing to its read-assist feature, the proposed scheme offers 38% improvement in bitline differential voltage and 40% reduction in cell data level degradation. View full abstract»

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  • Synthesizable delay line architectures for digitally controlled voltage regulators

    Publication Year: 2012 , Page(s): 72 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    This paper introduces a new architecture for a fully synthesizable digital delay line (DDL) used in digitally controlled voltage regulators. The new architecture uses a variable number of delay elements to lock to the clock frequency depending on the actual process corner and the temperature variations. Also, a comparison between the proposed scheme and the conventional delay line with discretely programmable delay cells is presented. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32 nm technology. The comparison shows that the proposed architecture has better linearity, area, and a fast calibration time with respect to conventional delay lines. View full abstract»

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  • A novel design flow for a 3D heterogeneous system prototyping platform

    Publication Year: 2012 , Page(s): 78 - 82
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3390 KB) |  | HTML iconHTML  

    This paper presents a novel design flow for three-dimensional (3D) heterogeneous system prototyping platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. Based on system partition and tri-state interface connecting, the MorPACK system can be efficiently extended by system bus interfaces and can improve the functions by only updating the bare die/module. In addition, the total silicon prototyping cost of heterogeneous SoC projects can be greatly reduced by sharing the MorPACK common system platform. To demonstrate the effectiveness of the proposed platform, six SoC projects are implemented. The results show that there are 79.13% fabrication cost reduced by the MorPACK platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited. View full abstract»

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