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Date 12-13 Nov. 2012

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Displaying Results 1 - 25 of 56
  • Design of power efficient FPGA based hardware accelerators for financial applications

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation to the execution on a CPU. The experimental results show that impressive results, in terms of speed-up and energy savings, can be obtained by using FPGA-based accelerators at expenses of a longer development time. View full abstract»

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  • Architectural trends in GHz speed DACs

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (969 KB) |  | HTML iconHTML  

    Recent interests from the research community in building digitized transmitters has led to numerous architectural and circuit-level developments in the design of digital-to-analog converters (DACs) in the GHz space. Several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the achievable speed and performance numbers. This paper aims to provide the reader with some of the emerging architectural innovations that address these challenges and aid in the transition of DACs into the GHz regime. View full abstract»

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  • A continuous-time IR-UWB RAKE receiver for coherent symbol detection

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1829 KB) |  | HTML iconHTML  

    Impulse radio ultra-wide band (IR-UWB) technology has been an interesting area of research for low power short-range applications. Due to wide bandwidth, RAKE based receivers are preferred over other type of receivers. However, designing RAKE based correlating receivers remains quite challenging. Correlating receivers in digital domain are very power consuming due to the high-speed DSPs, ADC and matched filter. Synchronization is another issue. Hence we get rid of these power hungry blocks in the presented correlating RAKE receiver which does coherent symbol detection in continuous-time without the need for synchronized clocks. A IR-UWB RAKE receiver in continuous-time binary value (CTBV) overcoming some of the fundamental issues of the conventional correlating receiver is presented along with the measured results. The IR-UWB RAKE receiver along with the sampler, symbol generator and ranging block can be used as a high-precision ranging and communication transceiver for biomedical applications. View full abstract»

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  • A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1606 KB) |  | HTML iconHTML  

    This paper presents a 3-5 GHz, high output amplitude, carrier-less based Ultra Wideband (UWB) transmitter for wirelessly powered RFID application. The UWB transmitter consists of a baseband pulse generator, a driver amplifier and an output on-chip filter. The baseband pulse generator and the driver amplifier are designed as zero DC power consuming circuit, which enables scalable power with the pulse rate. IC pad and bonding wire parasitics are considered to be absorbed as part of output filtering network, realizing package co-design. The simulation result shows that the proposed transmitter radiates 2.34 pJ/pulse energy with 1.63 V pulse amplitude. The total energy consumption under 1.8 V power supply is 18 pJ/pulse, corresponding to 13% energy efficiency. View full abstract»

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  • A 26 GHz UWB CMOS IR-UWB transmitter with on-chip balun

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2338 KB) |  | HTML iconHTML  

    A 22-29 GHz UWB pulse transmitter in 90 nm bulk CMOS is presented. The transmitter is based on mixing of a continuous running LC-tank 26 GHz signal with a pseudo Gaussian base-band pulse. To maximize pulse peak to peak voltage a single balanced Gilbert cell mixer is loaded with a lumped balun. The measured results show a pulse with a -10 dB bandwidth of 5 GHz and a Vp-p of 219 mV within the 22-29 GHz band. View full abstract»

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  • H.264/AVC motion estimation on FPGAs and GPUs: A comparative study

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (693 KB) |  | HTML iconHTML  

    Video compression has been receiving much deserved attention due to the widespread adoption of digital video technology, and the need of optimizing the storage and transmission of such media. In this paper, we are concerned with the optimization of one step of the H.264 compression standard, namely, the motion estimation, in which motion vectors coding the movement of macroblocks (or sub-macroblocks) between two frames are computed. Specifically, we present here a comparative study between two architectures that were used to implement the full search (FS) algorithm for single pixel precision according to the standard H.264/AVC. We are particularly concerned with the relation area × throughput of the two architectures. We report here on experiments performed on CIF, SD and full HD data, comparing the maximum throughput achieved and bandwidth required by the architectures. View full abstract»

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  • FPGA implementation of elementary generalized unitary rotation with CORDIC based architecture

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (747 KB) |  | HTML iconHTML  

    This paper describes the first trial of implementation of generalized unitary Jacobi-like rotation (the device is called EGU-rotator, further referred to as rotator) purely based on the CORDIC algorithm into Altera's and Xilinx FPGAs. The basics and examples for factorization of the generalized rotation matrix (further, matrix) are given. The number of matrix shapes alternates in the range from 4 to 64 depending on the range of used angles (parameters). A unified algorithm for implementation of parametrical rotator is provided. Reconfigurable architecture of rotator is briefly described. The choice of architecture is determined by 3 addresses and they correspond to different shapes of the matrix. The comparison of device resources for different wordlengths, the number of CORDIC iterations and platforms is given. The complex rotator works approximately 3 times slower and consumes approximately 5 times more device resources than a single CORDIC rotator. View full abstract»

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  • Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (605 KB) |  | HTML iconHTML  

    This paper presents a low-complexity energy efficient channel pre-processing update scheme, targeting the emerging 3GPP long term evolution advanced (LTE-A) downlink. Upon channel matrix renewals, the number of explicit QR decompositions (QRD) and channel matrix inversions are reduced since only the upper triangular matrices R and R-1 are updated, based on an on-line update decision mechanism. The proposed channel pre-processing updater has been designed as a dedicated unit in a 65 nm CMOS technology, resulting in a core area of 0.242mm2 (equivalent gate count of 116K). Running at a 330MHz clock, each QRD or R-1 update consumes 4 or 2 times less energy compared to one exact state-of-the-art QRD in open literature. View full abstract»

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  • Modeling and design of a dual-residue pipelined ADC in 130nm CMOS

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    A 9-bit 50MS/s dual-residue pipelined ADC is modeled and analyzed. The first stage is a modified pipelined ADC stage, while the other stages use an interpolator to resolve the signal; the focus is on designing these stages. A new successive approximation based interpolator (SAI) is proposed. This interpolator is insensitive to parasitic capacitances, and makes it possible to utilize open loop residue amplifiers. The dual-residue architecture is insensitive to the gain of the residue amplifiers, and only a matching between two amplifiers is necessary. Limiting parameters of the ADC are the offset in the residue amplifiers, as well as gain mismatch between the amplifiers. The ADC with the SAI got an ENOB of 8.99-bit when simulated without offset and gain mismatch. The maximum allowed offset voltage of the residue amplifier is equation, and with this offset voltage for all the amplifiers in the ADC the ENOB dropped to 8.61-bit. The maximum allowable mismatch between the two residue amplifiers is equation, with this mismatch the ENOB is 8.85-bit. Both these demands should be possible to reach without the use of calibration. With a zero-crossing based amplifier the last 8 stages of the ADC has an estimated power consumption of 2.1mW. View full abstract»

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  • A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2229 KB) |  | HTML iconHTML  

    In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency. At a sample rate of 50MS/s and a supply voltage of 1V, the 9-bit SAR ADC achieves an ENOB of 8.84 bit and consumes 45 μW, resulting in an energy efficiency of 2.01 fJ/conversion-step. The circuits are designed and simulated with parasitic models using a commercially available 28nm bulk CMOS process. View full abstract»

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  • KL-cut based digital circuit remapping

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (665 KB) |  | HTML iconHTML  

    This paper introduces the concept of k and kl-cuts on top of digital mapped circuits in netlist representations. Such new approach is derived from the concept of k and kl-cuts on top of And-Inverter Graphs (AIGs), respecting the differences between these two representations. The main motivation to use kl-cuts on top of mapped circuits is to perform local optimization. An algorithm for enumerating kl-feasible cuts on top of mapped circuits is proposed. A remapping approach is also presented. Preliminary results show that this approach is able to reduce up to 19% in area and up to 24% in delay of mapped circuits from a subset of ISCAS'85 benchmarks. View full abstract»

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  • Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures

    Publication Year: 2012 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1700 KB) |  | HTML iconHTML  

    A new algorithm for optimal register allocation in context of high-level synthesis is presented. In this paper we show how the greedy left-edge algorithm can be leveraged to obtain a globally optimal allocation, that is computed in polynomial time. By splitting variables at block boundaries, allows for allocation to be done using only quasi-local and local allocation - avoiding the complexity of true global allocation. As local allocation is much simpler than global allocation, this approach emphasizes efficiency and ease of implementation - at a cost of an increased number of register transfers compared to other allocators. Experiments show that runtime is linear for all practical purposes. View full abstract»

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  • A Novel on-chip ultra-low power temperature sensing scheme

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (999 KB) |  | HTML iconHTML  

    In this work, a CMOS based temperature sensor with Nano-watt power consumption is presented. The proposed scheme utilizes sensitivity of MOS towards temperature in subthreshold region. Sensor is composed of PMOS and NMOS group which subsequently generates voltages that are having positive and negative temperature coefficients respectively. It has been observed that on subtracting these voltages, resultant shows, highly linear dependence with temperature. The proposed scheme is implemented using AMS 0.35 μm standard CMOS technology, and it shows wide temperature sensing ranges from -40 °C to +140 °C with a power consumption of tens of Nano watts. View full abstract»

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  • Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    In this paper we present the design of a 0.18 μm CMOS current reference, which is very robust with respect to process variations (1.4% relative standard deviation measured over 23 samples) and with low power consumption of 290 nW. This result was obtained with devices that have low intrinsic sensitivity to process variability, such as diffusion resistors in a nanopower “classic” BJT-based bandgap topology. At the cost of a larger die area, we obtain a significant reduction of dispersion with respect to the best results available in the literature, with a low power consumption. View full abstract»

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  • Low power Real Time Clock with high accuracy over large supply voltage range

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1197 KB) |  | HTML iconHTML  

    Low-power Real Time Clock (RTC) circuits are important parts in a variety of modern applications. In addition to the low power-consumption, the frequency stability of the oscillation circuit and the whole RTC is important. We propose a RTC circuit that shows a deviation between -95ppm and 3.27ppm of the oscillation frequency from the mean value. The Measurements have been carried out over a manufactured split lot (therefore including local and global corner variations) and over a supply voltage range from 1.6V up to 2.5V. View full abstract»

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  • Memory-aware system scenario approach energy impact

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB) |  | HTML iconHTML  

    System scenario methodologies propose the use of different scenarios, e.g., different platform configurations, in order to exploit variations in computational and memory needs during the lifetime of an application. In this paper several extensions are proposed for a system scenario based methodology with a focus on improving memory organisation. The conventional methodology targets mostly execution time while this work aims at including memory costs into the exploration. The effectiveness of the proposed extensions is demonstrated and tested using two real applications, which are dynamic and suitable for execution on modern embedded systems. Reductions in memory energy consumption of 40 to 70% is shown. View full abstract»

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  • Configurable RTL model for level-1 caches

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (607 KB) |  | HTML iconHTML  

    Level-1 (L1) cache memories are complex circuits that tightly integrate memory, logic, and state machines near the processor datapath. During the design of a processor-based system, many different cache configurations that vary in, for example, size, associativity, and replacement policies, need to be evaluated in order to maximize performance or power efficiency. Since the implementation of each cache memory is a time-consuming and error-prone process, a configurable and synthesizable model is very useful as it helps to generate a range of caches in a quick and reproducible manner. Comprising both a data and instruction cache, the RTL cache model that we present in this paper has a wide array of configurable parameters. Apart from different cache size parameters, the model also supports different replacement policies, associativities, and data write policies. The model is written in VHDL and fits different processors in ASICs and FPGAs. To show the usefulness of the model, we provide an example of cache configuration exploration. View full abstract»

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  • Novel SRAM bias control circuits for a low power L1 data cache

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1205 KB) |  | HTML iconHTML  

    This paper proposes two novel bias control circuits to manage the power consumption of inactive cache cells in data retention mode. Both circuits have lower power consumption and area overheads when compared to previous proposals. The first proposed circuit (Dynamic Bias Control circuit or DB-Control circuit) dynamically tracks the reference current and sets the bias voltage of cells, while the second (Self-Adjust Bias Control circuit or SAB-Control circuit) has a self-adjust property to set the bias voltages and also alleviates the instability problems that appear due to noise injection. Although any SRAM array can benefit from these circuits, to show their usefulness, we frame our study on a recently proposed dual-versioning L1 data cache that has been designed for chip multi-processors that implement optimistic concurrency proposals, where leakage current has more effect on power dissipation and on circuit instability. Therefore, we add the proposed bias control circuits to a 32KB dual-versioning SRAM (dvSRAM) cache and simulate and optimize the entire cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage. The simulations demonstrate the effectiveness of our proposed circuits to reduce the energy consumption of dvSRAM L1 data cache by 35.8% on average compared to the typical dvSRAM cache. This is achieved with a modest area increase of 1.6% per sub-array and negligible delay overhead. We also show that instability problems are alleviated by using the SAB-Control circuit. View full abstract»

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  • An operational amplifier for high performance pipelined ADCs in 65nm CMOS

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1182 KB) |  | HTML iconHTML  

    A CMOS fully differential high gain-bandwidth (GBW) product operational amplifier (OpAmp) is presented in this paper. In order to achieve a high gain, the Nested gain-boosting technique [1] is employed. The design is implemented in a 1.1V standard 65nm CMOS process. The DC-gain of the OpAmp is larger than 77.9dB with the unity-gain frequency of 4.61GHz while achieving 76.2 degrees of phase margin (PM). Applying the maximum input swing, the output signal settles to 0.01% accuracy in less than 3.8ns. The output total harmonic distortion (THD) of the OpAmp is 0.586% for maximum signal swing at the frequencies near Nyquist frequency with the input-referred noise of 5.4nV/√Hz. The high GBW product of this design makes it suitable for 12-bit 200MS/s pipelined ADC applications. View full abstract»

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  • Analyses of single-stage complementary self-biased CMOS differential amplifiers

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1422 KB) |  | HTML iconHTML  

    This paper analyzes and compares two complementary self-biased CMOS differential amplifiers. The two amplifiers differ only in terms of the number of output nodes, namely one is single-ended, the other being fully differential. Furthermore, the amplifiers are completely self-biased embedding the negative feedback in the biasing loop which makes them highly resistant to process, supply voltage and temperature variations. Both circuits are analyzed on the basis of small signals and expressions for gain are derived. The two amplifier topologies are simulated yielding a good match between the obtained results and the theory. Finally, discussed amplifiers featuring high gain and PVT immunity are well-suitable for implementation in nanometer CMOS processes. View full abstract»

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  • Heart and respiratory detection and simulations for tracking humans based on respiration by using pulse-based radar

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (793 KB) |  | HTML iconHTML  

    In this paper we present experimental findings of both the heart and respiratory rate of a static person using pulse based radar and we present a simulated system for tracking a moving person based on respiratory motion in an indoor environment. In the simulation the subject moves in one dimension and the system is able to track the subject by detecting their respiration. The presented system contains a transmitter, receiver, and channel model section, in addition to control section which controls the transceiver and processes the received data. The Gaussian monocycle is considered as transmitted pulse and the channel is modeled based on multipath delay and attenuation. The system first removes the person's movement using correlation between each received wave form. Then, the respiration rate of the target is calculated. Finally, the respiration rate is used to track the specific target in an indoor environment. The system is effective for accurate tracking of subjects walking in one direction, under 10 m/s. The algorithm for finding heart and respiratory rates is the same for both real and simulated environments. View full abstract»

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  • Implementation of FPGA based DSP module for CW Doppler radar: Preliminary results

    Publication Year: 2012 , Page(s): 1 - 6
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    This paper presents development and implementation of the Field-Programmable Gate Arrays (FPGA) of a novel Digital Signal Processing (DSP) module for the 24 GHz continuous wave (CW) Doppler radar. The module utilizes the well-known zero-crossing algorithm, relative simple signal filtering, iterative search method and the scattering centers model. The module is constructed to detect vehicles; it estimates its velocity, lane, and shape. Preliminary results of the lane and vehicle length estimation in case of two lanes are provided. VHDL code has been generated and necessary FGPA device resources for basic stages of DSP are estimated. Implementable VDHL code generation of novel algorithm is based on Simulink HDL coder. View full abstract»

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  • A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1139 KB) |  | HTML iconHTML  

    This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 μW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit. View full abstract»

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  • Power efficient arrangement of oversampling sigma-delta DAC

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2525 KB) |  | HTML iconHTML  

    A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations. View full abstract»

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  • A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    Two branches of gated ring oscillators (GRO) act as the delay lines in 2-dimension Vernier time-to-digital converter (TDC). The proposed architecture reduces dramatically the inherent latency of vernier structure. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been simulated in 90nm CMOS technology. Operating from 50MHz reference frequency, it achieves a resolution better than 2ps assuming a signal bandwidth of 1.56MHz (OSR=16), for a minimum current consumption of 1.8mA from 1.2V. View full abstract»

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