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Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Date 23-23 Oct. 1998

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  • 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

    Publication Year: 1998
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  • A VLSI design of a pipeline FFT in GF(256)

    Publication Year: 1998 , Page(s): 373 - 376
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    A pipeline VLSI design of FFT based on Good-Thomas algorithm is presented. To implement FFT with 255 points in GF(256), this design only needs 60 eight bits galois multipliers, a ROM to store 30 twiddles and some registers. The latency is 255+17 clock cycles, and the maximum combination delay is the sum of one multiplier in GF(256) and four stage XOR gates. This design is modular, regular, simple and suitable for VLSI implementation View full abstract»

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  • Discussion on the low-power CMOS latches and flip-flops

    Publication Year: 1998 , Page(s): 477 - 480
    Cited by:  Papers (1)
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    Latches and flip-flops used in low power circuits are discussed in this paper. Two kinds of latches of 5-T and 4-T are evolved from the standard 8-T static latch for low power application. Simulation results show that the 4-T latch has the lowest power consumption with no speed penalty. The 4-T latch is usually considered as dynamic. However, detailed analysis shows that it may be static under certain conditions, which are also given in this paper. Single-edge-trigged (SET) flip-flops and double-edge-trigged (DET) flip-flop based on these latches are also presented. Significant power and area savings can achieve by using 4-T latches. View full abstract»

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  • Discussion on the optical-coupling in silicon optical-type micromechanical sensors

    Publication Year: 1998 , Page(s): 953 - 956
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    A flow-sensor and a resonator are fabricated on silicon substrate using the micromechanical technology. The devices are with a structure based on a silicon cantilever with waveguide on the surface to detect the movement of the silicon cantilever. The method to couple the laser into the waveguide is discussed and the performance of the fabricated devices are characterized. View full abstract»

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  • Author index

    Publication Year: 1998 , Page(s): 962 - 973
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  • A study of EOS failures in power IGBT modules

    Publication Year: 1998 , Page(s): 152 - 155
    Cited by:  Papers (1)
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    The influences of electrical overstress (EOS) on the reliability of power-insulated gate bipolar transistor (IGBT) modules were investigated by switching, frequency, and blocking tests. This paper reports the test results and the failure analysis results. Some conclusions, from the point of IGBT application reliability view, are also provided in this paper View full abstract»

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  • Microstructure and fatigue resistance of solder interfaces

    Publication Year: 1998
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    Summary form only given. The relationship between microstructure and fatigue resistance of solder interfaces was studied by examining micromechanisms and micromechanics of fatigue crack growth along a series of model interfaces. While the fatigue crack was seen to prefer staying in the solder when propagating at high rates, interfacial crack sliding was predominant in the near-threshold regime. A micromechanical model of interfacial crack sliding was developed, based on the interface fracture mechanics concept View full abstract»

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  • The control of pattern distortion and drift in epitaxial layer

    Publication Year: 1998 , Page(s): 139 - 140
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    The orientation deviation is the main factor influencing pattern distortion in epitaxial buried layers on p-type ⟨100⟩ silicon substrate. It is pointed out that better patterns can be obtained by deviating the orientation of the p-type ⟨100⟩ wafer 2°~3° from the ⟨100⟩ axis toward the nearest ⟨110⟩ axis. This is somewhat different from the commonly adopted epitaxial growth condition View full abstract»

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  • Self-heating effect in SOI MOSFETs

    Publication Year: 1998 , Page(s): 572 - 574
    Cited by:  Papers (5)
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    Self-heating effect in SOI MOSFETs affects the carrier mobility, SOI MOSFETs threshold voltage and the band gap of silicon in channel. The mechanism of heat generation and heat dissipation in SOI MOSFETs is analyzed in this paper on the basis of which a simple self-heating effect model is established. The model introduces only one factor related with self-heating effect whose value can be easily determined according to the device structure parameters. The model is also verified experimentally View full abstract»

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  • Quantum resonant tunneling effect and multi-value logic memory

    Publication Year: 1998 , Page(s): 588 - 589
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    A novel fabrication process, based on selective wet etching and GaAs air-bridge was developed to produce AlAs/GaAs, AlAs/InAs/GaAs quantum dots double barrier quantum well sub-micron resonant tunneling diodes (RTD), and the peak to valley current ratio could be over 20. A new model of multilevel logic SRAM with RTDs was proposed View full abstract»

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  • Physical properties of semiconducting transition metal silicides and their prospects in Si-based device applications

    Publication Year: 1998 , Page(s): 247 - 250
    Cited by:  Patents (5)
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    Semiconducting transition metal silicides are of interest as potential candidates for new Si-based devices. The recent advances obtained on the understanding of the physical properties of this group of materials are summarized with special emphasis on β-FeSi2 . Characteristic features of the electronic structure are outlined. Interband and infrared optical properties are in good agreement with theoretical predictions. Light emission could be observed from implanted β-FeSi2 layers only. Incorporation of corresponding dopants gives n- and p-type material. Carrier interaction with nonpolar optical and acoustic phonons as well as neutral impurities has to be taken into account. The problems and prospects of application of semiconducting silicides are discussed View full abstract»

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  • 290 V high voltage NMOSFET with two different doping level drift regions by compatible 1.5 μm CMOS technology

    Publication Year: 1998 , Page(s): 145 - 148
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    This paper reports on a novel device, a high voltage NMOSFET with two different doping level drift regions. The device is compatible with 1.5 μm CMOS technology. The two different doped regions are formed with n well implantation and n field implantation in standard CMOS process. The experimental result shows that the die breakdown voltage of this NMOSFET is from 120 V to 290 V according to different structures, such as drift length and drift doping level View full abstract»

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  • AlGaAs/InGaAs PHEMT preamplifier for optical communication systems

    Publication Year: 1998 , Page(s): 594 - 597
    Cited by:  Papers (1)
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    The design, fabrication and characteristics of a AlGaAs/InGaAs PHEMT monolithic transimpedance preamplifier is described. The PHEMT material used here is based on δ-doped carrier supplying layer and GaAs/AlGaAs superlattice buffer. The transconductance and output conductance of a 1 μm-gate PHEMT is 250 mS/mm and 8mS/mm respectively with threshold voltage of -1.2 v, the maximum saturation current density is 235 mS/mm. On-wafer network analysis with HP8510 network analyzer shows its cut-off frequency of 21 GHz and maximum oscillation frequency of 40 GHz. Transimpedance preamplifier its measured maximum transimpedance gain of 51.4 dBΩ with -3 dB bandwidth no less than 5.05 GHz. The input equivalent-noise current density is 13 PA/√Hz View full abstract»

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  • CMOS performance and density trends as we approach 0.1 μm

    Publication Year: 1998 , Page(s): 6 - 9
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    The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 μm is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement View full abstract»

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  • The recent TEM application development for microelectronics

    Publication Year: 1998 , Page(s): 315 - 318
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    Transmission electron microscopy (TEM) has played an important role in silicon VLSI/ULSI process evaluation and failure analysis. More recently, it has also been applied to micro-electro-machine system (MEMS), MCM, ...etc. In this talk, a few recent TEM application developments are presented. Some of these TEM applications may seem very difficult or impossible previously. These new applications are made possible by innovative sample preparation break through View full abstract»

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  • Low pressure growth of diamond films under fluorine addition

    Publication Year: 1998 , Page(s): 800 - 802
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    Phase diagrams in the C-H-F system for low pressure diamond growth have been calculated in the usual conditions: 0.1-6.67 kPa, 900-1100 K, and the agreements with experiments are good. A series of ternary phase diagrams imply that the suitable composition for low pressure diamond growth in C-H-F system is confined in the small CH4-H-HF triangle. There is no diamond growth region while F/(F+H)>0.5, only a HF-CF4 line appears. The diamond growth region changes greatly with substrate temperature and fluorine concentration View full abstract»

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  • Micro electromechanical systems (MEMS): technology and future applications in circuits

    Publication Year: 1998 , Page(s): 928 - 931
    Cited by:  Papers (1)
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    MEMS technology can enable new circuit components. Current examples include RF signal switches, tunable capacitors and inductors, resonant filters, antennas, and relays. These components, all involving micromechanical principles, can provide enhanced performances and reconfigurability, reduced component sizes, and potentially simplified system-level design. I will discuss our DARPA-funded efforts in developing electromechanical RF switches, high-gain antennas, and new types of planar waveguides. Thermal-mechanical RF switches exhibit low on-state insertion loss and high off-state isolation compared with conventional transistor-based counterparts, while operating under IC-compatible bias conditions View full abstract»

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  • Device physics, performance simulations and measured results of SOI MOS and DTMOS transistors and integrated circuits

    Publication Year: 1998 , Page(s): 712 - 715
    Cited by:  Papers (3)
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    A dynamic threshold MOSFET (DTMOS) was invented by Assaderaghi et al.(1994), connecting the gate to the contact terminal. There are four ways to connect the contact terminal: (1) keep the contact terminal floating; (2) connect the contact terminal to the source; (3) connect the contact terminal to the gate; and (4) take the contact terminal as a new input. We have designed fabricated and simulated all four ways of connecting the contact terminal View full abstract»

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  • The investigation of recessed channel SOI devices

    Publication Year: 1998 , Page(s): 720 - 723
    Cited by:  Patents (2)
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    Recessed channel SOI devices were investigated. In this paper, the structure and processing of such devices is described in detail. The characteristics of a SOI MOSFET using recessed channel technology are much better than normal thick non-depleted and thin-film fully depleted SOI MOSFETs. The 0.15~4.0 μm recessed channel SOI MOSFETs with a silicon channel film of 70 nm and a source/drain silicon film of 160 nm are developed using a submicron process. The transconductance and drain current are increased by 40% more than thin-film fully depleted SOI MOSFETs View full abstract»

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  • CMOS scaling towards its limits

    Publication Year: 1998 , Page(s): 31 - 34
    Cited by:  Papers (4)
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    CMOS LSIs are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, CMOS scaling towards its limits are explained based on the experimental results of the downsizing MOSFET into such dimension, and further concept for deep-sub-0.1 μm CMOS is described View full abstract»

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  • Quadru-tree algorithm for transition probability in CMOS IC power estimation

    Publication Year: 1998 , Page(s): 492 - 495
    Cited by:  Patents (1)
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    A new Quadru-Tree algorithm, by which the transition probabilities of circuit nodes, including all internal and output nodes, can be exactly worked out, and its program implementation are presented in this paper. As evidence of its accuracy and efficiency, the result of one example run in the prototype is reported, as well View full abstract»

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  • Electrically active defects in surface preamorphized and subsequently RTP-annealed Si and the effect of titanium silicidation

    Publication Year: 1998 , Page(s): 324 - 327
    Cited by:  Patents (6)
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    Thermal evolution of ion implantation-induced defects and the influence of concurrent titanium silicidation in pre-amorphized p-type Si (implanted with 25 keV, 1016 cm-2 Si+) under rapid thermal processing (RTP) have been studied. Ion implantation-induced electrically active defects have been detected by deep level transient spectroscopy (DLTS), capacitance-temperature (C-T), and spreading resistance measurements. DLTS characterization results show that the thermal evolution of electrically active defects in self-ion (Si+) implanted Si depends critically on the post-implantation thermal anneal: Hole traps H1(0.33 eV) and H4(0.47 eV) appear after the highest temperature (950°C) RTP anneal, while a single trap H3(0.26 eV) level shows up at lower anneal temperatures (⩽900°C). The thermal signature of H 4 defect is very similar to that of iron interstitial while those of H1 and H3 levels appear to originate from some interstitial-related defects, possibly complexes. A complete elimination of the above interstitial-related defects with concurrent RTP Ti silicidation has been observed, apparently a result of vacancy injection. The paper will present details of defect evolution under various conditions of RTP for samples with and without the silicidation View full abstract»

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  • Electronic structure and properties of novel thermoelectrics from first principles calculations

    Publication Year: 1998 , Page(s): 856 - 859
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    The application of first principles calculations based on density functional theory to novel thermoelectric materials is discussed. These calculations give an understanding of the electronic structure and transport coefficients that is often complementary to the view provided by experimental characterization efforts, and which is often useful in identifying promising materials and guiding their optimization. This is illustrated by examples in the skutterudites View full abstract»

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  • Lead zirconate titanate thin films on GaAs for microwave device applications

    Publication Year: 1998
    Cited by:  Patents (1)
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    Summary form only given. Bulk Acoustic Wave (BAW) resonant devices based on quartz crystals are widely used in electronic systems at frequencies up to a few tens of MHz. However for operation at higher frequencies the crystal must be made much thinner and consequently-ceases to be mechanically self supporting. Similarly, Surface Acoustic Wave (SAW) device dimensions shrink at high frequencies requiring sub-micron electrode structures for microwave operation. In this paper we describe how the submicron critical dimensionality of acoustic wave devices can be achieved by depositing thin piezo-ceramic films on semiconductor substrates with the subsequent fabrication of BAW devices. The piezoelectric ceramic used in this work is sol-gel derived lead zirconate titanate (PZT) about 0.5 μm thick. Films having the composition Pb(Zr0.53Ti0.47)O3, have been prepared on platinized silicon (Pt-Si) and platinized gallium arsenide (Pt-GaAs) substrates using a 1,3-propanediol and a novel 1,1,1-tris(hydroxymethyl)ethane based sol-gel technique. Crystallisation of the PZT films on the Pt-GaAs was achieved by firing the sol-gel coating at 650°C for a dwell time of 1 second using rapid thermal processing (RTP) techniques. Films having the required thickness of ~0.5 μm were produced from a single deposition of the precursor sol resulted. Average values of remnant polarisation (Pr) for the Films were 29 μC/cm2 and 24 μC/cm2 on Pt-Si and Pt-GaAs respectively, comparing very well with bulk values. Preliminary microwave characterisation performed on PZT/Pt-Si based BAW resonator structures indicates a fundamental parallel resonance at 0.1 GHz, having an unloaded Q of 1100. Higher frequency operation will be obtained when substrate thinning under the active layer has been optimised View full abstract»

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  • Numerical simulation of semiconductor devices considering self-heating effects

    Publication Year: 1998 , Page(s): 472 - 475
    Cited by:  Papers (1)
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    Electro-thermal simulation, which considers the influence of self-heating effects an semiconductor devices, is becoming more and more important. But as the popular device simulator, PISCES-2ET needs a big improvement in order to realize simulation including lattice temperature, since the simulator has paid more attention to carrier temperature rather than lattice temperature. This paper presents an electro-thermal device simulation program which is developed on the basis of the device simulation program PISCES-2H. In comparison with PISCES-2ET, our program includes the influence of lattice temperature on Poisson's equation and the electric field, providing additional thermal boundary conditions and temperature dependent models. Furthermore, two additional numerical methods are adopted according to the characteristics of the electro-thermal simulation in our program. They are more suitable for simulation considering self-heating effects than the common Gummel and full Newton methods View full abstract»

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