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Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Date 9-10 Aug. 1999

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  • Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing

    Publication Year: 1999
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    Freely Available from IEEE
  • Author index

    Publication Year: 1999 , Page(s): 131
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    Freely Available from IEEE
  • Determining redundancy requirements for memory arrays with critical area analysis

    Publication Year: 1999 , Page(s): 48 - 53
    Cited by:  Papers (8)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations View full abstract»

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  • A tribute to graphics DRAMs

    Publication Year: 1999 , Page(s): 123 - 130
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    High speed graphics subsystems used some of the earliest application specific DRAMs. Knowledge gained from working with these specialized parts has provided a background for many of the innovations seen today in high speed DRAMs, fast core DRAMs, and high bandwidth embedded DRAMs. Years before synchronous DRAMs become common, clocked DRAM field memories for television frame buffers were in production. The later Video DRAMs were precursors for EDO page mode, dual bank architecture, synchronous operation, and high bandwidth through use of a wide internal bus. Implementations for graphics subsystems today continue to spearhead the emerging area of embedded DRAMs and parallel processing View full abstract»

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  • Built in self test for ring addressed FIFOs with transparent latches

    Publication Year: 1999 , Page(s): 72 - 77
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    The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches for applications that require high data rates. The method used is compared to previous results for ring addressed FIFOs with edge triggered input latches. Several different special test modes are used to provide both more efficient and more complete BIST View full abstract»

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  • Low-power SRAM circuit design

    Publication Year: 1999 , Page(s): 115 - 122
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on high-capacitance predecode lines, write bus lines and datalines, AC current reduction by using multistage decoding, operating voltage reduction coupled with low-power sensing by using charge-transfer amplification, step-down boosted word-line scheme or full current-mode read/write operation and leakage current suppression by using dual-Vt, Auto-Backgate-Controlled multiple-Vt, or dynamic leakage cut-off techniques View full abstract»

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  • A fast test to generate flash memory threshold voltage distribution map

    Publication Year: 1999 , Page(s): 78 - 82
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    This paper describes a method to determine threshold voltage (V th) distribution as a multi-colored bitmap of the die. That is, a visual indication of relative threshold voltages on different areas of the die is provided. The spatial distribution of threshold voltage is felt to be more informative than conventional techniques which provide results as a bell-curve Gauss distribution plot of threshold voltage versus number of cells. The time required for test execution (including data gathering) is considerably less than the time taken by conventional methods View full abstract»

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  • Failure mechanisms detected in memory chips during routine construction analysis

    Publication Year: 1999 , Page(s): 34 - 39
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    Construction analysis is a useful tool to determine microcircuit structure and identify potential failure mechanisms. Cross sectioning procedures used in construction analysis have revealed two possible failure mechanisms. One mechanism involving the use of SOG results in poor adhesion and delamination. The other mechanism permits the corrosion of internal conductors through a combination of discontinuities in the passivation at growth boundaries and internal damage View full abstract»

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  • Modeling and testing transistor faults in content-addressable memories

    Publication Year: 1999 , Page(s): 83 - 90
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A behavioral analysis of transistor faults and cell-stuck-at faults in a n-word by l-bit static CMOS CAM array is presented. First, a CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine level. Then, a transistor stuck-(on/open) and cell-stuck-at fault model for a CAM is defined. We show that two out of eighteen possible CAM cell's transistor faults cannot be tested reliably by functional tests; however among faults that are testable, are all those which comprise data-retention faults. We also show that a test, originally designed to detect input stuck-at faults, also detects all reliably testable transistor faults and all cell-stuck-at faults in the model View full abstract»

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  • A comparative simulation study of four multilevel DRAMs

    Publication Year: 1999 , Page(s): 102 - 109
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1636 KB)  

    Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. (1989) and the noise cancellation techniques of a MLDRAM proposed by Gillingham (1996). Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons View full abstract»

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  • Designing a memory module tester

    Publication Year: 1999 , Page(s): 91 - 98
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000 View full abstract»

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  • Computing in memory architectures for digital image processing

    Publication Year: 1999 , Page(s): 8 - 15
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    Continuing improvements in semiconductor fabrication density are enabling new classes of system-on-a-chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing performance, flexibility, manufacturability, and fabrication cost View full abstract»

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  • Tutorial: characterizing SDRAMs

    Publication Year: 1999 , Page(s): 62 - 69
    Cited by:  Papers (1)
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    This paper presents characterization methods for an SDRAM in a manufacturing environment. Contact tests, dc tests, basic functional tests, signal margin tests and retention characterization are shown. Measurement of the cell signal is used as an example for pico probing. Special test modes for SDRAMs which can be used to aid characterization and failure analysis (FA) are discussed View full abstract»

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  • The potential of carbon-based memory systems

    Publication Year: 1999 , Page(s): 110 - 114
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    It seems likely that density concerns will force the DRAM community to consider using radically different schemes for the implementation of memory devices. We propose using nano-scale carbon structures as the basis for a memory device. A single-wall carbon nanotube would contain a charged buckyball. That buckyball will stick tightly to one end of the tube or the other. We assign the bit value of the device depending on which side of the tube the ball is. The result is a high-speed, non-volatile bit of memory. We propose a number of schemes for the interconnection of these devices and examine some of the known electrical issues View full abstract»

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  • Design validation of .18 μm 1 GHz cache and register arrays

    Publication Year: 1999 , Page(s): 54 - 60
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    This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 μm 7LM copper BEOL technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (i) SRAM operability in product-like clocking and ABIST environments. (ii) Demonstration of yield using 2-dimensional redundancy. (iii) Characterization of SRAM signals used in the macro timing rules. (iv) Obtain high volume pre-product manufacturing test experience. (v) Verify SRAM functionality at technology stress test conditions. Prototype test chips in IBM's .18 μm technology have provided opportunities to investigate these areas, greatly mitigate risks associated with ever decreasing product design cycles and exercise the SRAM timing rules and logic models in a product-like application View full abstract»

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  • Interconnect diagnosis of bus-connected multi-RAM systems

    Publication Year: 1999 , Page(s): 40 - 47
    Cited by:  Papers (1)
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    This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ) View full abstract»

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  • The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval

    Publication Year: 1999 , Page(s): 24 - 31
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1576 KB)  

    Dynamic Associative Access Memory (DAAM) chips are processor-in-memory chips wherein a large number of small processing elements are put in a DRAM's sense amps. Thousands of these chips will be mounted on “memory boards” in “TONY” full-text database servers. This paper shows that multibank memory eliminates DRAM latency, and a one-bit ALU that can be made into an associative processor, with the addition of one gate. This paper shows how this unconventional technology offers nearly three orders of magnitude better cost performance than a Pentium microprocessor, nearly 1,000 MIPs per dollar of chip cost for the DAAM compared to about 1 MIPs per dollar of chip cost for the Pentium. This paper shows that a TONY server system using this chip will handle over a million on-line users, more than two orders of magnitude more cost-effective than the best current database machines, and a TONY server stores a page of text for approximately five cents (the cost of duplicating the printed page) View full abstract»

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  • Unbalanced cache systems

    Publication Year: 1999 , Page(s): 16 - 23
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    The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at a particular level is fixed, it is easily shown that at least one divided cache structure exists for which the miss-rate is the same as a single unified cache. By using alternate implementations, however, the method may provide a significant decrease in miss-rates as is shown via simulations. Specifically, SPEC95 benchmarks are used to demonstrate that the technique is effective for general usage but it may be even more useful for embedded systems where memory access patterns can be more fully controlled (i.e. via the compiler). In addition to improved miss-rates, another advantage is that the hit-time for multiple smaller caches may be smaller than for a single larger cache. Disadvantageous, but readily surmountable, electrical aspects are also discussed View full abstract»

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