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Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Date 19-21 Feb. 1992

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  • 1992 IEEE International Solid-State Circuits Conference. Digest of Technical Papers [Front Cover]

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    Freely Available from IEEE
  • Micromechanisms fabrication: a challenge in micromechanics and microelectronics

    Page(s): 14 - 17
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    Micromechanisms fall into two broad categories: sensors and actuators. Actuators convert electric energy to mechanical energy, whereas sensors convert physical quantities such as force and pressure to electronic signals. The sensor area, in particular the resonating sensor, appears to have the earmarks of practical applications. These applications are not in just the traditional pressure-transducer area, but extend to new magnetic devices, humidity sensors, and gas-flow monitors. Micromechanical systems benefit from available microelectronic technologies if magnetic rather than electrostatic drives are used with reasonable-gap dimensions. It is noted that demonstration of a fully-fed-back system is only a few months away. Identified applications in magnetic recording, microsurgery, and precision positioning appear to provide, a healthy, economically viable future for this field.<> View full abstract»

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  • Future automotive electronic systems and their impact on solid-state-circuits

    Page(s): 20 - 22
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    The current status of automobile electronics is surveyed, and the relationship between automobile electronics and the semiconductor industry is examined. To achieve the evolution of the auto electronic system described, progress in three major areas of semiconductor technology is necessary: (1) power single chip microcomputers are needed for the computing center; (2) combined logic and power devices are needed for remote electronics in intelligent peripherals, and (3) new packaging technologies are required for semiconductor devices in these peripherals. It is concluded that, to achieve the necessary objectives, a much better understanding of the mutual problems in the semiconductor and the auto industry is necessary. The auto industry must have a better understanding of the semiconductor learning curve, and the technological progress that can be made over time. The semiconductor industry, where progress is mainly driven by the demands of the computer business, should spend more resources on, meeting the special requirements of the auto industry.<> View full abstract»

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  • Personal communications: Quo vadis

    Page(s): 24 - 26
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    The author predicts at least four major stages in the evolution of personal communication services (PCS). Stage one will include isolated PCS islands/experiments proprietary technologies, some dedicated or shared frequency spectra and limited services. Stage two will include limited interoperability, initial industry coalitions, some dedicated or shared frequency spectra, and more services. Stages one and two cover the period 1992-2000. Stage three will include widespread interworking, stable spectrum assignments, broad industry coalitions, personal numbers, and standard services. Stage four includes adequate spectrum/capacity, national interfaces, stable industry structure, widespread personal numbers, and mass-market services. Stages three and four cover the period 2000-2005.<> View full abstract»

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  • An 8 b 650 MHz folding ADC

    Page(s): 30 - 31
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    Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation.<> View full abstract»

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  • A 10 b 50 MS/s pipelined ADC

    Page(s): 32 - 33
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    Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.<> View full abstract»

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  • A 12 b 20 MS/s ripple-through ADC

    Page(s): 34 - 35
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    The characteristics of a 12 b 20 MS/s ripple through analog-to-digital converter (ADC) are described. The one-bit-per-stage ripple-through architecture used in this 12-b ADC requires only 21 comparators and one track and hold for 12-b resolution, resulting in a smaller die (18 mm/sup 2/) and 7 to 14 dB better signal to noise and distortion ratio (SNDR) than previous 10-b converters.<> View full abstract»

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  • A 12 b 5 MS/s two-step CMOS A/D converter

    Page(s): 36 - 37
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    A 12 b 5 MHz fully differential two-step ADC (analog-to-digital converter) is described which is integrated in a 1- mu m CMOS technology, uses both analog and digital correction, and dissipates 200 mW. The ADC architecture and timing diagram are shown.<> View full abstract»

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  • A code-error calibrated two-step A/D converter

    Page(s): 38 - 39
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    A direct code-error calibration technique improving the linearity of two-step or multistep ADCs (analog-to-digital converters) is implemented in the digital domain. While conventional techniques calibrate code errors in the analog domain before conversion, the proposed technique calibrates digital outputs obtained by uncalibrated ADCs after conversion. This technique reduces feedthrough, offset, and interstage gain errors simultaneously. A block diagram of a digitally calibrated two-step flash ADC is shown. The experimental ADC uses a 2- mu m n-well CMOS technology.<> View full abstract»

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  • A 17 b algorithmic ADC

    Page(s): 40 - 41
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    An analog-to-digital converter (ADC) is presented which uses auto gain-ranging to achieve signal amplification without the associated amplification of input-referred errors. The part, fabricated in a BiCMOS process, has a 108-dB dynamic range limited by white noise and DC errors <20 mu V. The system consists of an input multiplexer, two sample and holds (SHAs), an error amplifier, precision resistor/switch network, a window comparator and a CMOS gate array. Systematic offsets in the SHAs, noise in the loop, and gain accuracies (determined by resistor ratios) are the critical design parameters. The design challenge is to optimize the noise within the system bandwidth and remove all nonlinear forms of error. Performance in the time domain when a decaying exponential voltage with an 80-ms time constant is applied at the input is shown.<> View full abstract»

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  • An oversampling converter for strain gauge transducers

    Page(s): 42 - 43
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    Oversampling converters with digital filters tailored to remove line-frequency interference have recently been introduced to DC measurement. The authors extend the approach to address the problems of low-noise amplification, drift and aging, and interference modulation. The block diagram of the monolithic system is shown. The 1/f noise of the converter is removed through chopper stabilization. Transducer AC excitation and chopper stabilization remove drift components due to thermocouples and amplifier offsets, respectively. Chip performance is summarized.<> View full abstract»

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  • 0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

    Page(s): 46 - 47
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    BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5- mu m BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.<> View full abstract»

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  • A 1.5 V full-swing BiCMOS logic circuit

    Page(s): 48 - 49
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    A full-swing BiCMOS logic circuit is described which operates twice as fast as CMOS, even at 1.5 V supply. Transient-saturation of bipolar junction transistors (BJTs) enables high-speed operation below 2 V. This BiCMOS circuit is based on the concept of saturating the BJTs only when they drive the load, enabling full-swing operation without speed degradation. The configuration of the proposed BiCMOS circuit is shown, and simulation results are presented.<> View full abstract»

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  • A PLL clock generator with 5 to 110 MHz lock range for microprocessors

    Page(s): 50 - 51
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    The authors describe a phase-locked-loop (PLL)-based deskewed clock generator that is fully integrated with a microprocessor and achieves a skew of less than 0.1 ns with peak-to-peak jitter of 0.45 ns using an 0.8- mu m CMOS technology. The block diagram of the deskewed clock generator is shown along with the measured schmoo diagram of the PLL clock generator functionality frequency versus supply voltage.<> View full abstract»

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  • A system-integrate ULSI chip containing eleven 4 Mb RAMs, six 64 kb SRAMs and an 18 k gate array

    Page(s): 52 - 53
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    The authors describe the realization of a ULSI chip that makes system integration possible on a silicon die, not in wafer-scale integration. They consider chip configuration, packaging, defect relief, fabrication, and evaluation results. This system-integrated ULSI chip (SYSI-ULSI) contains eleven standard 4-Mb DRAMs, six standard 64-kb SRAMs, 200 I/O pins, and an 18-k gate array. The DRAMs are laid out on both sides of the chip. The 200 I/O pins are located on the upper and lower sides of the chip, and the gate array is laid out at the center to reduce the length of the channel between it and each part and eliminate skew between channels by equalizing their lengths. The 38.16*50.4 mm/sup 2/ SYSI-ULSI chip is packaged in a 324-pin 54*86 mm/sup 2/ plastic grid array package. A Cu/W thermal spreader is used for die-bonding. A cavity-down package is used for low thermal resistance with a heat sink. Power dissipation is 3.9 W.<> View full abstract»

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  • A 9.5 Gb/s Si bipolar ECL array

    Page(s): 54 - 55
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    The authors describe a 9.5-Gb/s Si bipolar ECL (emitter coupled logic) gate which has performance approximately equal to that of custom ICs because of optimized ECL circuit design, 0.3- mu m Si bipolar process, and 10-GHz package technology. 9.5-GHz operation is obtained with 1-mA switching current and 0.3*5.5 mu m/sup 2/ emitter area because emitter current density (J/sub e/) for shortest propagation time is 1.5 to 2.0 times as large as J/sub e/ for maximum f/sub T/. This ECL array was designed for multi-gigabit system operation and, in addition to digital, logic, and analog functions, it is easily configurable to provide high-speed functions such as clock distributors, shift registers, and ripple counters.<> View full abstract»

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  • A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

    Page(s): 56 - 57
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    A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches.<> View full abstract»

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  • A CMOS low-voltage-swing transmission-line transceiver

    Page(s): 58 - 59
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    A simplified representation of a bidirectional transmission line with I/O transceiver cells is shown. The drivers are open-drain n-channel devices and the receivers are differential comparators. When all drivers are inactive, the high-level signal is established by the terminator supply voltage. The loaded characteristic impedance of stripline signal traces on a printed-circuit board can be about 50 Omega . When there is more than one driver, the transmission line must be terminated at both ends to prevent reflections. System arbitration allows only one driver access to a line at any time. The load seen by each driver is about 25 Omega . The power dissipated is reduced if the signal voltage swing and the Vol level are small. The minimum voltage swing must be large enough to assure acceptable noise margin.<> View full abstract»

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  • A 32 Mb/s fully-integrated read channel for disk-drive applications

    Page(s): 62 - 63
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    The authors describe a mixed-signal ASIC (application-specific integrated circuit) which integrates the entire disk-drive and read channel by combining bipolar and CMOS circuit techniques and taking advantage of the inherent device properties of each. The chip contains approximately 10000 devices fabricated in a 1.5- mu m 5-V-only BiCMOS process and implements the traditional peak detector architecture supporting zoned-bit recording applications. The 800-mW worst-case power dissipation and pin count of 52 are achieved by reducing the off-chip component requirement to that of bypass and coupling capacitors, the loop filter components for the AGC, and the phase-locked loops. Integration of the continuous-time filter eliminates high-accuracy inductors or capacitors for the lowpass filter/equalizer/differentiator networks. On-chip sampling capacitors for the servo peaks maintain matching between servo channels.<> View full abstract»

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  • A 27 MHz programmable bipolar 0.05 degrees equiripple linear-phase lowpass filter

    Page(s): 64 - 65
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    A continuous-time transconductance-C filter which meets the requirement of the read channel of disk drives based on conventional peak detection pulse qualification is presented. To accommodate constant-density recording with variable data rates tip to 48 Mb/s, the cut-off frequency is tunable between 9 and 27 MHz. The filter is placed inside the AGC (automatic gain control) loop and its differential output signal amplitude is typically held at 1 V/sub PP/. Its primary role is to lower the achievable error rates by bandlimiting the noise originating in the magnetic media and the preamplifier. Its second objective is to equalize the bit stream. i.e. to slim the data pulses, allowing higher densities. To minimize pulse peak shifts in time, an accurate linear phase (or constant group delay) response over the signal bandwidth is essential. The transfer function implemented is seventh-order 0.05 degrees equiripple linear-phase. By allowing negligibly small ripple, the region of constant delay can be extended to about twice the cut-off frequency f/sub c/, compared to 1.5 f/sub c/ for a Bessel filter of equal order, traditionally used in this application. The tradeoff, however, is a nearly twofold increase in sensitivity to transconductance excess phase.<> View full abstract»

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  • A 10.7 MHz CMOS OTA-R-C bandpass filter with 68 dB dynamic range on-chip automatic tuning

    Page(s): 66 - 67
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    The authors report a maximally flat 10.7-MHz fourth-order bandpass filter with 68 dB dynamic range. The bandwidth and ripple of the filter are 250 kHz and 0.5 dB, respectively. The third intermodulation distortion is below -40 dB for fully differential input signals up to 3.4 V peak-to-peak. The supply voltages are +or-2.5 V. The filter architecture is based on two biquadratic sections in cascade.<> View full abstract»

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  • An implantable digital telemetry integrated circuit using an automatic resonant-frequency search technique

    Page(s): 68 - 69
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    An integrated circuit is presented which uses a voltage-controlled oscillator (VCO) and amplitude detector to search for the resonant frequency prior to each transmission, thus guaranteeing resonant operation despite variations in either antenna or integrated circuit characteristics. A block diagram of the transmitter is shown. The transmitter design is combined with a simpler on-off keying receiver and the necessary digital logic to support bidirectional digital telemetry.<> View full abstract»

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  • A 140 Mb/s 32-state radix-4 Viterbi decoder

    Page(s): 70 - 71
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    Applications in trellis code demodulation for communication channels and digital sequence detection for magnetic storage devices generate interest in implementation of the Viterbi algorithm at around 100 MHz. An important decoding problem found in both applications is the binary shift register trellis. The classical high-throughput implementation for such decoders is the radix-2 state-parallel approach, where add-compare-select (ACS) units are assigned to each state and organized in pairs to iterate one stage of a 2-state trellis. The decode rate is fundamentally limited by either the recursive ACS iteration or the recursive traceback iteration. To date, such single-chip implementations have been limited to a decode rate of 25 Mb/s. In the present work, the throughput has been extended in an area-efficient manner by applying one stage of lookahead to both the ACS and traceback recursions. This architecture is demonstrated in a 32-state, radix-4 Viterbi decoder achieving 140 Mb/s decode rate.<> View full abstract»

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  • A video digital signal processor with a vector-pipeline architecture

    Page(s): 72 - 73
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    A description is given of a 2-GOPS, 60-MIPS video digital signal processor ULSI with a vector-pipeline architecture for video CODEC systems, called the vector digital signal processor (VDSP). The VDSP uses 0.8- mu m CMOS technology and contains a discrete cosine transform (DCT) core as a special processing unit. The vector-pipeline (VP) architecture allows input vector data to be processed in various pipeline configurations. The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261. The encoder and the decoder specified in the subset including the applications of CCIT H.261 (full-CIF mode at 15 frame/s or more, 64 kb/s) can be realized with only two VDSP chips, and only one VDSP chip, respectively, and thus have twice the performance of prior digital signal processors.<> View full abstract»

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  • A reconfigurable multiprocessor IC for prototyping of real-time data paths

    Page(s): 74 - 75
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    In real-time digital-signal processing systems, data often enter or leave the computationally intensive parts at small integer multiples of the clocking interval. In these cases, traditional microprocessor-based architectures are inadequate to meet the throughput requirements, and so clusters of dedicated data paths, hard-wired to closely match the algorithmic data flow, are often used. These architectures typically contain multiple concurrently operating data-path pipelines. The circuit reported targets the rapid implementation and prototyping of such architectures using reconfigurable multiprocessors. This circuit contains eight execution units (EXUs) connected via a dynamically controlled crossbar switch. It can operate at 25 MHz (200 MIPs) with a data I/O bandwidth of 400 MB/s and a typical power consumption of 0.45 W. It contains 140106 transistors on a 8.9*9.5 mm/sup 2/ die, in 1.2- mu m CMOS technology.<> View full abstract»

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